CMOS半導體製程概念 INVERTER.

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Presentation transcript:

CMOS半導體製程概念 INVERTER

Inverter Process Steps P-SUBSTRATE (a) field oxide etching

Inverter Process Steps P-SUBSTRATE N-WELL (b) N-well diffusion

Inverter Process Steps P-SUBSTRATE N-WELL (c) field oxide etching

Inverter Process Steps P-SUBSTRATE N-WELL (d) gate oxidation

Inverter Process Steps P-SUBSTRATE N-WELL (e) polysilicon definition

Inverter Process Steps P-SUBSTRATE N-WELL p+ (f) n-plus diffusion n+ n+

Inverter Process Steps (g) p-plus diffusion P-SUBSTRATE N-WELL n+ p+ n+ n+ p+ p+

Inverter Process Steps P-SUBSTRATE N-WELL n+ p+ (h) oxide growth n+ n+ p+ p+

Inverter Process Steps P-SUBSTRATE N-WELL n+ p+ (i) contact cuts n+ n+ p+ p+

Inverter Process Steps (j) metal N-WELL n+ p+ P-SUBSTRATE n+ n+ p+ p+

Simplified CMOS Inverter Process cut line n type substrate - p well/tub n well

Ｎ-Well Mask After p-well use implants to adjust VTn

Active Mask Grown thick oxide. Then use active mask to create thin oxide layers over the active areas – where we are going to place the transistors (source, gate, and drain areas)

Poly Mask First used chemical deposition to deposit polysilicon on wafer. Note thin oxide area for gate oxide - critical (helps determine Vth) doe 0.25 micron technology -> 6.5 to 5.5 microns thick

Ｎ+ Select Mask Followed by diffusion (ion implant) to build pfets source and drain areas

Ｐ+ Select Mask Followed by diffusion (ion implant) to build nfets source and drain areas

Contact Mask After deposition of SiO2 insulator, then contact holes are etched (in this case to make contacts to source and drain regions)

Metal Mask 62 processing steps for a double/twin tub CMOS process!! tanqueray.eecs.berkeley.edu/~ehab/inv.html

Layout Inverter佈局繪製動畫說明圖例 P substrate poly wafer n well