\course\cpeg323-05F\Topic6b-323 Pipeline Control 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 Assumptions PC is updated at each cycle Pipeline registers are also updated at each cycle Only need to set control values during each pipeline stage 2018/12/6 \course\cpeg323-05F\Topic6b-323

Five Groups of Control Lines 1. Instruction Fetch: The control signals to read instruction memory and to write the PC are always asserted, so there is nothing special to control in this pipeline stage. 2. Instruction Decode/Register Fetch: As in the previous stage, the same thing happens at every clock cycle, so there are no optional control lines to set. 3. Execution: The signals to be set are RegDst, ALUop, and ALUSrc. The signals select the Result register, the ALU operation, and either a register or a sign-extended immediate for the ALU. 2018/12/6 \course\cpeg323-05F\Topic6b-323

Five Groups of Control Lines (Cont’d) 4. Memory Stage: The control lines set in this stage are Branch, MemRead, and MemWrite. These signals are set by the branch equal, load, and store instructions, respectively. 5. Write Back: The two control lines are MemtoReg, which decides between sending the ALU result or the memory value to the registers, and Reg-Write, which writes the chosen value. 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 A copy of Figure 6.26 from page 468 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 A copy of Figure 6.27 from page 468 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 The values of the control lines are the same as in Figure5.20, but they have been shuffled into three group corresponding to the last three pipeline stages. 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 The Control Lines for the Final Three Stages 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 The pipelined datapath, with the control signals connected to the control portions of the pipeline registers. The control values for the last three stages are created during the instruction decode stage and then placed in the ID/EX pipeline register. The control lines for each pipe stage are used, and remaining control lines are then passed to the next pipeline stage. 2018/12/6 \course\cpeg323-05F\Topic6b-323

Hazards and Hazards Resolution Hazards detection Hazards resolution 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 (cont’d) Hazards: situations that prevent the next instruction in the instruction stream to be executed at the designated clock cycle. 2018/12/6 \course\cpeg323-05F\Topic6b-323

Hazards (structral and data) (cont’d) Hazards (structral and data) Structural: Resource conflicts when hardware cannot support all possible combinations of instructions in simultaneous overlapped execution Data: Instructions depend on the results of a previous instruction in a way that is exposed by the overlapping execution. 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 (cont’d) Hazards (control) Control: Due to branches and other instructions that change PC Hazard will cause “stall”, but in pipeline “stall” is serious - it will hold multiple instructions. It stalls later instructions, not earlier instructions. 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 Hazards (cont’d) Structural Hazards Non-pipelined FUs One port of a R-file One port of M. Data hazards for some data hazards ( e.g. ALU/ALU ops): forwards (bypass) 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 Data Hazards (cont’d) for others: pipeline interlock + pipeline stall (bypass cannot do on time) LD R1 A + R4 R1 R7 this may need a “stall” or bubble 2018/12/6 \course\cpeg323-05F\Topic6b-323

Example of Structural Hazard Instruction Clock cycle number 1 2 3 4 5 6 7 8 9 Load instruction IF ID EX MEM WB Instruction i+1 IF ID EX MEM WB Instruction i+2 IF ID EX MEM WB Instruction i+3 stall IF ID EX MEM WB Instruction i+4 IF ID EX MEM A pipeline stalled for a structural hazard-a load with one memory port. With only one memory port, the pipeline cannot initiate a data fetch and instruction fetch in the same cycle. A load instruction effectively steals an instructin-fetch cycle, causing the pipeline to stall - no instruction is initiated on clock cycle 4 (which normally would be instruction i+3). Because the instruction being fetched is stalled, all other instructions in the pipeline can proceed normally. The stall cycle will continue to pass through the pipeline. 2018/12/6 \course\cpeg323-05F\Topic6b-323

Why ALUOUTPUT has a “1” in IF? PC IF ID EX MEM WB M R a ALU op IF ID EX MEM WB PC Unit 1 R 1 1 ALU 1 ALU OUTPUT 1 1 M 1 1 Why ALUOUTPUT has a “1” in IF? 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 Pipelined dependencies in a five-instruction sequence using simplified datapaths to show the dependencies. 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 The dependencies between the pipeline registers move forward in time, so it is possible to supply the inputs to the ALU needed by the and instruction and or instruction by forwarding the results found in the pipeline registers. 2018/12/6 \course\cpeg323-05F\Topic6b-323

Data Hazard Resolution Software method Architecture features 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 A B + C . E A + D Flow-dependency (R/W conflicts) 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 A B + C . A B - C Output dependency (W/W conflicts) Leave A in wrong state if order is changed 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 X A + B . A C + D anti-dependency (W/R conflicts) 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 How about arrays? . A [i] = = A[i-1]+.. RAW (read after write) - j tries to read a source before i writes it, so j incorrectly gets the old value. This is the most common type of hazard. WAR (write after read) - j tries to write a destination before it is read by i, so i incorrectly gets the new value. This cannot happen in our example pipeline because all reads are early (in ID) and all writes are late (in WB). This hazard occurs when there are some instructions that write results early in the instruction pipeline, and other instructions that read a source after a write of an instruction later in the pipeline. For example, autoincrement addressing can create a WAR hazard. WAW (write after write) - j tries to write an operand before it is written by i. The writes end up being performed in the wrong order, leaving the value written by i rather than the value written by j in the destination. This hazard is present only in pipelines that write in more than one pipe stage (or allow an instruction to proceed even when a previous instruction is stalled). The DLX pipeline writes a register only in WB and avoids this class of hazards. 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 j i MIPS Read / Read Write / Write no Read / Write yes Write /Read no “Shared Datum” conflicts This case is different from the situation with back-to-back ALU operations. The LW instructioan does not have the data until the end of the MEM cycle., while the ADD instruction needs to have the data by the beginning of that clock cycle. Thus, the data hazard from using the result of a load instruction cannot be completely eliminated with simple hardware. We can forward the result immediately to the ALU from the MDR and for the SUB instruction - which begins two clock cycles after the load - the result arrives in time, as shown in ?. However, for the ADD instruction, the forwarded result arrives too late - at the end of a clock cycle though it is needed at the beginning. LW R1, 32 (R6) IF ID EX MEM WB ADD R4, R1, R7 IF ID EX MEM SUB R5, R1, R8 IF ID EX AND R6, R1, R7 IF ID Pipeline hazard occurring when the result of a load instruction is used by the next instruction as a source operand and is forwarded. The value is avaiable when it returns from memory at the end of the load instructions’s MEM cycle. However, it is needed at the beginning of that clock cycle for the ADD (the EX stage of the add). The load value can be forwarded to the SUB instruction and will arrive in time for that instruction (EX). The AND can simply read the value during ID since it reads the registers in the second half of the cycle and the value is written in the first half. 2018/12/6 \course\cpeg323-05F\Topic6b-323

\course\cpeg323-05F\Topic6b-323 Data Dependence S1 S1: $R1 = $R2 + 1 S2: $R3 = $R1 + $R4 S3: $R4 = $R1 – 2 S4: $R3 = 2 S2 S3 Dependences: S1, S2 -> flow-dependence S1, S3 -> flow-dependence S2, S3 -> anti-dependence S2, S4 -> output-dependence S4 2018/12/6 \course\cpeg323-05F\Topic6b-323