Incrementing and Decrementing

Slides:



Advertisements
Similar presentations
L23 – Adder Architectures. Adders  Carry Lookahead adder  Carry select adder (staged)  Carry Multiplexed Adder  Ref: text Unit 15 9/2/2012 – ECE 3561.
Advertisements

Combinational Logic Design
CS 140 Lecture 14 Professor CK Cheng 11/14/02. Part II. Standard Modules A.Interconnect B.Operators. Adders Multiplier Adders1. Representation of numbers.
Homework Reading Machine Projects Labs
Combinational circuits
9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Binary additon & subtraction.
9/15/09 - L22 Sequential Circuit Design Copyright Joanne DeGroat, ECE, OSU1 Sequential Circuit Design Creating a sequential circuit to address a.
Part 2: DESIGN CIRCUIT. LOGIC CIRCUIT DESIGN x y z F F = x + y’z x y z F Truth Table Boolean Function.
L23 – Arithmetic Logic Units. Arithmetic Logic Units (ALU)  Modern ALU design  ALU is heart of datapath  Ref: text Unit 15 9/2/2012 – ECE 3561 Lect.
9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Decoders and Multiplexers.
9/15/09 - L6 Standard FormsCopyright Joanne DeGroat, ECE, OSU1 Standard Forms.
9/15/09 - L27 CountersCopyright Joanne DeGroat, ECE, OSU1 Final Exam Review Exam Time: MONDAY o dark 30 7:30AM this room.
1/8/ L3 Data Path DesignCopyright Joanne DeGroat, ECE, OSU1 ALUs and Data Paths Subtitle: How to design the data path of a processor.
1/8/ L11 Project Step 5Copyright Joanne DeGroat, ECE, OSU1 Project Step 5 Step 2 in behavioral modeling. Use of procedures.
9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits.
Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Logic and Computer Design.
L26 – Datapath ALU implementation
Arithmetic Functions BIL- 223 Logic Circuit Design Ege University Department of Computer Engineering.
9/15/09 - L4 Combinational Logic - Gates Copyright Joanne DeGroat, ECE, OSU1 Combinational Logic Circuits – Gates.
9/15/09 - L21 Sequential Circuit Analaysis Copyright Joanne DeGroat, ECE, OSU1 Sequential Circuit Analysis.
9/15/09 - L24 Other FF TypesCopyright Joanne DeGroat, ECE, OSU1 Other FF Types.
9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits.
9/15/09 - L26 Shift RegistersCopyright Joanne DeGroat, ECE, OSU1 Shift Registers.
1 Lecture 12 Time/space trade offs Adders. 2 Time vs. speed: Linear chain 8-input OR function with 2-input gates Gates: 7 Max delay: 7.
CS 151: Digital Design Chapter 4: Arithmetic Functions and Circuits
CHAPTER 2 Digital Combinational Logic/Arithmetic Circuits
9/15/09 - L19 Sequential CircuitsCopyright Joanne DeGroat, ECE, OSU1 Sequential Cirucits.
MicroBaby ALU.
ECE 3110: Introduction to Digital Systems
Computer System Design Lecture 3
Combinational Circuits and Boolean
Combinational Circuits
ECE 3130 Digital Electronics and Design
Subtitle: How to design the data path of a processor.
ECE 4110– Sequential Logic Design
Swamynathan.S.M AP/ECE/SNSCT
Homework Reading Machine Projects Labs
Copyright Joanne DeGroat, ECE, OSU
Reference: Moris Mano 4th Edition Chapter 4
XOR, XNOR, and Binary Adders
CSE Winter 2001 – Arithmetic Unit - 1
HALF ADDER FULL ADDER Half Subtractor.
XOR, XNOR, & Binary Adders
MicroBaby Datapath.
Number Systems and Circuits for Addition
L25 – Datapath ALU.
MicroBaby Datapath.
Homework Reading Machine Projects Labs
Overview Part 1 – Design Procedure Part 2 – Combinational Logic
Step 2 in behavioral modeling. Use of procedures.
L11 – Midterm Review.
XOR, XNOR, and Binary Adders
ECE 352 Digital System Fundamentals
Combinational Circuits
ECE 352 Digital System Fundamentals
Special Gates Combinational Logic Gates
XOR Function Logic Symbol  Description  Truth Table 
L11 – State Machine Analysis
Structural Modeling and the Generate Statement
Arithmetic Circuits.
Step 2 in behavioral modeling. Use of procedures.
L4 – An overview of Quartis
© Copyright Joanne DeGroat, ECE, OSU
XOR, XNOR, and Binary Adders
2's Complement Arithmetic
Instruction execution and ALU
Copyright Joanne DeGroat, ECE, OSU
Structural Modeling and the Generate Statement
Presentation transcript:

Incrementing and Decrementing 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU

Class 18a – Special arithmetic circ. Incrementers Decrementers Circuits Material from section 4-5of text 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU

Copyright 2009 - Joanne DeGroat, ECE, OSU Incrementer Often just want to increment the value by 1 and that is the only operation needed. An incrementer is a circuit that is much simpler than an adder. Start with the equations: SUM = A xor B xor Cin Cout = AB + ACin + BCin 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU

Copyright 2009 - Joanne DeGroat, ECE, OSU Incrementer Often we just want a circuit to create the value +1 each time. The circuit is a significant simplification. Start with the equations for general addition Sum = A Å B Å Cin Cout = AB + BCin + ACin Now if B = 0 these reduce to IncSum = A Å Cin Inc Carry= A0 + B0 + ACin = ACin A Half Adder!!! 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU

Copyright 2009 - Joanne DeGroat, ECE, OSU Implementation A increment unit Note that hardware can be simplified if you have a unit that always increments. 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU

Copyright 2009 - Joanne DeGroat, ECE, OSU A Decrementer Want to subtract 1 from the input. reduces to What are the equations Difference D=AÅBÅBorin reduces to AÅBorin Borrow-out Bout= BBorin + A’B+A’Borin Reduces to Bout = A’Borin 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU

Copyright 2009 - Joanne DeGroat, ECE, OSU The circuit And again can do a dedicated circuit And again can do a multiple bit implementation with simplification of the lsb and msb. 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU

Copyright 2009 - Joanne DeGroat, ECE, OSU Class 18a assignment Covered sections 4-5 Problems for hand in none Problems for practice Reading for next class: sections 5-1, 5-2 9/15/09 - L15 Decoders, Multiplexers Copyright 2009 - Joanne DeGroat, ECE, OSU