Separate Compilation of Hierarchical Real-Time Programs into Linear-Bounded Embedded Machine Code Arkadeb GHOSAL, UC Berkeley Christoph KIRSCH, University.

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Separate Compilation of Hierarchical Real-Time Programs into Linear-Bounded Embedded Machine Code Arkadeb GHOSAL, UC Berkeley Christoph KIRSCH, University of Salzburg Thomas HENZINGER, EPFL Alberto SANGIOVANNI-VINCENTELLI, UC Berkeley Daniel IERCAN Politehnica University of Timisoara APGES – October 4 th, 2007, Salzburg

2 Introduction Linear-bounded target code as parallelism and hierarchy of real-time program are increased Modular compiling algorithm

3 Flat vs. Hierarchical Compilation FlatHierarchical

4 Case Study T1 T3 T2 Perturbation Taps Interconnection Taps P1 P2

5 Controller Design No Perturbation => I P controller No Perturbation => PT1 PI controller T1 – P controller || T2 – P controller T1 – P controller || T2 – PI controller T1 – PI controller || T2 – P controller T1 – PI controller || T2 – PI controller

6 Code 2b Code 2a Code 1b Code 1a One Tank System Controller (Hierarchy) Flat Code Timing t controller hpump 500 Hierarchical Code PI Functionality controller 3: release(PI) 4: future(500, 3) 5: return 0: release(P) 1: future(500, 0) 2: return 3: release(PI) 4: future(500, 3) 5: return 0: release(P) 1: future(500, 0) 2: return Logical Execution Time = 500 P

7 Three Tanks System Controller (Parallelism) Functionality Timing t controller_1 h_1pump_1 500 controller_2 h_2pump_2 Logical Execution Time = 500 PI_1 controller_1 P_1PI_2 controller_2 P_2

8 Code 2d Code 2b Code 2c Code 2a Code 1d Code 1c Code 1b Code 1a Flat Code Hierarchical Code 0: release(P_1) 1: future(500, 0) 2: return 0: release(P_1) 1: release(P_2) 2: future(500, 0) 3: return 8: release(P_1) 9: release(PI_2) 10: future(500, 8) 11: return 4: release(PI_1) 5: release(P_2) 6: future(500, 4) 7: return 12: release(PI_1) 13: release(PI_2) 14: future(500, 12) 15: return 6: release(P_2) 7: future(500, 6) 8: return 3: release(PI_1) 4: future(500, 3) 5: return 9: release(PI_2) 10: future(500, 9) 11: return Code Generation T1 controllerT2 controller

9 Hierarchy Level = 10 Number of Modules = 12 Number of Switches = 2 Hierarchy Level = 8 Number of Modules = 8 Number of Switches = 3 Flat Compiler Hierarchical Compiler Worst Case Code Size Comparison

10 Related Work Code generation for Timed Languages –Giotto and TDL are restricted to one level of periodic tasks –Code generation for TM does not explicitly address the hierarchical structure Code generation for Synchronous Languages –Simulink-to-SCADE/Lustre-to-TTA, generates code for a target time- triggered architecture. –Taxys generates an application specific scheduler that ensures timing commitment of tasks Our code generation technique uses hierarchical structure and generates code for a virtual machine

11 Conclusion Compiler for hierarchical real-time program Linear bounded code Modular Compiler Low runtime overhead The full implementation and a demo video are available at:

12 Thank you!!!