ELEC-7250 VLSI Testing Scan Design Implementation on ISCAS ’89 Benchmark Circuits – s1423 and s1512 Completed by: Jonathan Harris.

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Presentation transcript:

ELEC-7250 VLSI Testing Scan Design Implementation on ISCAS ’89 Benchmark Circuits – s1423 and s1512 Completed by: Jonathan Harris

What is Scan Design? Combinational Logic PI’s PO’s PO or Scan Out 1 Scan In Clock D Q dffn dff2 dff1 Scan Mode 00110011 00101011

Scan Design – Pros & Cons Disadvantages Gate and area overhead Performance penalty – 2 gate delays Long test application time Advantages High Fault Coverage Minimal Test Generation Time Easily Automated

s1423 and s1512 s1423 s1512 # Primary Inputs 17 29 # Primary Outputs 5 21 # Gates 557 780 # Flip-Flops 74 57 % Scan Overhead 22.8% 16.9%

Scan Design Results Total Faults Undet. Fault Coverage # Gates Test Time (min) circuit s1423 w/o scan 1663 946 47.78% 731 19 pseudo-scan 27 98.38% 32 full scan 2131 98.73% 1027 726 s1512 1411 1364 22.86% 837 14 68 95.18% 23 1761 95.14% 1025 487

Project Demo and Questions