SRC Exception Processing Mechanism Interrupt Request ireq: Interrupt Acknowldge iack: Disable Interrupt Flag IE: Get interrupt Info. Isrc-info <15…0> Load PC with Exception Vector Ivect<31…0> Save PC in IPC<31...0>

Behavioral RTL for Exception Processing Instruction_interpretation:= (!Run&Strt: Run  1: Run & !(ireq&IE):(IR M[PC], PC  PC + 4; Instruction_execution), Run&(ireq&IE): (IPC  PC<31..0>, II<15..0>  Isrc_info<15..0>, IE  0: PC  Ivect<31..0>, Iack  1; Iack  0) , Instruction_interpretation); Meaning Start Normal Fetch Interrupt, PC copied II is loaded with the info. PC loaded with new address

Additional Instructions to support interrupts mnemonic Behavioral RTL Meaning svi (op=16) R[ra]<15..0>  II<15..0>, R[rb]  IPC<31..0>; Save II and IPC ri (op=17) II<15..0>  R[ra]<15..0>, IPC<31..0>  R[rb]; Restore II and IPC een (op=10) IE  1; Exception enable edi (op=11) IE  0; Exception disable rfi (op=30) PC  IPC, IE  1; Return from interrupt

Structural RTL for Exception Processing Step Concrete RTN TO (!(ireq&IE): (MA  PC, C  PC + 4); (ireq&IE): (IPC  PC,II Isrc_info, IE  0,PC  22α 0©Isrc_vect<7..0> © 00,iack  1;iack  0,End); T1 MD  M[MA],PC  C; T2 IR  MD; T3 Instruction_execution;

Combining the RTL for reset and exception Instruction interpretation:= Events Run&!Rst&!(ireq&IE):(IR  M[PC], PC  PC+4; Normal Fetch Run&Rst:( Rst 0 , IE  0, PC  0 Soft Reset !Run&Strt:(Run 1, PC  0, R[0..31]  0; Hard Reset Run&!Rst&(ireq&IE):(IPC  PC<31..0>, II<15..0>  Isrc_info<15..0>,IE  0, PC  Ivect<31..0>,iack  1; iack  0; Interrupt

Executing machine instructions with and without pipelining Fetch Inst. Operand ALU Operation Memory Access Register Write add r4, r2, r3 Without Pipelining Only one functional unit busy Fetch Inst. Fetch Operand ALU Operation Memory Access Register Write ld r1, a st r2, b add r4, r2, r3 sub r6, r7, r5 shl r1, r2, 4 All functional units busy With Pipelining

Pipeline Stages 5 pipeline stages are shown 1. Fetch instruction ld r1, a 5 pipeline stages are shown 1. Fetch instruction 2. Fetch operands 3. ALU operation 4. Memory access 5. Register write 5 instructions are executing 1. ld r1, a ; memory access 2. st r2, b ; idle 3. add r4, r2, r3 ; ALU op 4. sub r6, r7, r5 ; idle 5. shr r1, r2, 4 ; write back Fetch Operand st r2, b ALU Operation add r4, r2, r3 Memory Access sub r6, r7, r5 Register Write shr r1, r2, 4

Pipeline Stages: alternate notation Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Ifetch Reg/Dec Exec Mem Wr lw Ifetch: Instruction Fetch Reg/Dec: Operand Fetch and Instruction Decode Exec: ALU operation Mem: Memory access stage Wr: Write the data back to the register file

Dependence Example Consider the following two instructions going through the pipeline as shown add r3, r2, r1 sub r4, r5, r3 r3 is the destination written in 5th stage r3 is the operand required in 2nd stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Ifetch Reg/Dec Exec Mem Wr add r3, r2, r1 Ifetch Reg/Dec Exec Mem Wr sub r4, r5, r3

Branch and Load Delay example Branch Delay brzr r2, r3 add r6, r7, r8 ;This instruction is always executed st r6, addr1 ;Only done if r2 ≠0 Load Delay ld r2,addr add r5, r1, r2 ;This instruction gets “old”value of r2 shr r1,r1,4 sub r6, r8, r2 ;This instruction gets r2 value loaded from addr

Review

CS501 Advanced Computer Architecture Lecture18 Dr.Noor Muhammad Sheikh

CS501 Advanced Computer Architecture

Exceptions

Bandwidth and Latency

Pipelining

Pipeline Design Requirements

Pipelining Stalls