Inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 23 – Representations of Combinatorial Logic Circuits 2006-10-20 TA/Punner.

Slides:



Advertisements
Similar presentations
Hardware Implementations Gates and Circuits. Three Main Gates  AND  OR  NOT.
Advertisements

CS61C L16 Representations of Combinatorial Logic Circuits (1) Beamer, Summer 2007 © UCB Scott Beamer Instructor inst.eecs.berkeley.edu/~cs61c CS61C :
CS61C L15 Representations of Combinatorial Logic Circuits (1) Garcia, Fall 2005 © UCB Lecturer PSOE, new dad Dan Garcia
CS61C L22 Representations of Combinatorial Logic Circuits (1) Garcia © UCB Lecturer PSOE Dan Garcia inst.eecs.berkeley.edu/~cs61c.
CS 61C L13 Combinational Logic (1) A Carle, Summer 2005 © UCB inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #13: Combinational.
CS 61C L29 Combinational Logic Blocks (1) Garcia, Spring 2004 © UCB Lecturer PSOE Dan Garcia inst.eecs.berkeley.edu/~cs61c.
CS61C L23 Combinational Logic Blocks (1) Garcia © UCB Lecturer PSOE Dan Garcia inst.eecs.berkeley.edu/~cs61c CS61C : Machine.
CS61C L23 Combinational Logic Blocks (1) Garcia, Spring 2007 © UCB Salamander robot!  Swiss scientists have built a robot that can both swim and walk.
CS61C L21 State Elements: CircuitsThat Remember (1) Garcia © UCB Lecturer PSOE Dan Garcia inst.eecs.berkeley.edu/~cs61c.
Gates and Circuits. Three Main Gates  AND  OR  NOT.
CS 61C L14 State (1) A Carle, Summer 2005 © UCB inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #14: State and FSMs Andy.
CS 61C L14 Combinational Logic (1) A Carle, Summer 2006 © UCB inst.eecs.berkeley.edu/~cs61c/su06 CS61C : Machine Structures Lecture #14: Combinational.
CS61C L21 State Elements : Circuits that Remember (1) Spring 2007 © UCB 161 Exabytes In 2006  In 2006 we created, captured, and replicated 161 exabytes.
CS61C L22 Representations of Combinatorial Logic Circuits (1) Garcia, Spring 2008 © UCB 100 MPG Car contest!  The X Prize Foundation has put up two prizes;
CS61C L21 State Elements : Circuits that Remember (1) Garcia, Fall 2006 © UCB One Laptop per Child  The OLPC project has been making news recently with.
CS61C L17 Combinatorial Logic Blocks (1) Beamer, Summer 2007 © UCB Scott Beamer, Instructor inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture.
CS61C L22 Representations of Combinatorial Logic Circuits (1) Eric, Spring 2010 © UCB Cal Alumni Wins 2009 Turing Award! Charles P. Thacker was named.
CS61C L24 Latches (1) Garcia © UCB Lecturer PSOE Dan Garcia inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture.
CS61C L18 Combinational Logic Blocks, Latches (1) Chae, Summer 2008 © UCB Albert Chae, Instructor inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures.
CS61C L23 Combinational Logic Blocks (1) Garcia, Fall 2006 © UCB Lecturer SOE Dan Garcia inst.eecs.berkeley.edu/~cs61c UC.
CS 61C L23 Combinational Logic Blocks (1) Garcia, Fall 2004 © UCB slashdot.org/article.pl?sid=04/10/21/ &tid=126&tid=216 Lecturer PSOE Dan Garcia.
CS 61C L15 Blocks (1) A Carle, Summer 2005 © UCB inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #15: Combinational Logic Blocks.
CS 61C L21 State Elements: CircuitsThat Remember (1) Garcia, Fall 2004 © UCB Lecturer PSOE Dan Garcia inst.eecs.berkeley.edu/~cs61c.
CS 61C L28 Representations of Combinatorial Logic Circuits (1) Garcia, Spring 2004 © UCB Lecturer PSOE Dan Garcia inst.eecs.berkeley.edu/~cs61c.
CS 61C L22 Representations of Combinatorial Logic Circuits (1) Garcia, Spring 2004 © UCB Lecturer PSOE Dan Garcia inst.eecs.berkeley.edu/~cs61c.
CS61C L17 Combinational Logic (1) Chae, Summer 2008 © UCB Albert Chae, Instructor inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #17.
Boolean Algebra and Truth Table The mathematics associated with binary number system (or logic) is call Boolean: –“0” and “1”, or “False” and “True” –Calculation.
CS61C L15 Synchronous Digital Systems (1) Beamer, Summer 2007 © UCB Scott Beamer, Instructor inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture.
CS 61C L15 State & Blocks (1) A Carle, Summer 2006 © UCB inst.eecs.berkeley.edu/~cs61c/su06 CS61C : Machine Structures Lecture #15: State 2 and Blocks.
CS61C L25 Representations of Combinational Logic Circuits (1) Garcia, Spring 2013 © UCB Android Brain on Robots!  “Half the weight of some robots is.
The Logic of Compound Statements
Fall 2012: FCM 708 Foundation I Lecture 2 Prof. Shamik Sengupta
Computer Science 210 Computer Organization Introduction to Boolean Algebra.
Sneha.  Gates Gates  Characteristics of gates Characteristics of gates  Basic Gates Basic Gates  AND Gate AND Gate  OR gate OR gate  NOT gate NOT.
Computer Organization and Design Lecture 16 – Combinational Logic Blocks Close call!   Cal squeaked by Washington in Overtime We win, and then.
CEC 220 Digital Circuit Design Boolean Algebra I Wed, Sept 2 CEC 220 Digital Circuit Design Slide 1 of 13.
CEC 220 Digital Circuit Design Boolean Algebra Friday, January 17 CEC 220 Digital Circuit Design Slide 1 of 22.
CS/COE0447 Computer Organization & Assembly Language
CS 61C L4.1.1 Combinational Logic (1) K. Meinz, Summer 2004 © UCB CS61C : Machine Structures Lecture Logic Gates and Combinational Logic
Fundamental Logic Gates And, Or, Not. Logic Gates: The Basics Regulate the flow of electricity within circuits to perform desired functionalities Each.
CS61C L24 State Elements : Circuits that Remember (1) Garcia, Fall 2014 © UCB Senior Lecturer SOE Dan Garcia inst.eecs.berkeley.edu/~cs61c.
Logic Simplification-Using Boolean Laws Logic Design Laboratory EE 2121 Lectures By Manesh T EE2121-In Charge
1 CS/COE0447 Computer Organization & Assembly Language Logic Design Appendix C.
Revisão de Circuitos Lógicos PARTE III. Review Use this table and techniques we learned to transform from 1 to another.
Discrete Structures for Computer Science Presented By: Andrew F. Conn Slides adapted from: Adam J. Lee Lecture #1: Introduction, Propositional Logic August.
Morgan Kaufmann Publishers
Logic Gates and Boolean Algebra
Flip Flops Lecture 10 CAP
Senior Lecturer SOE Dan Garcia
Boolean Algebra.
State Circuits : Circuits that Remember
There is one handout today at the front and back of the room!
Inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #21 State Elements: Circuits that Remember Hello to James Muerle in the.
Memristor memory on its way (hopefully)
Agenda – 2/12/18 Questions? Readings: CSI 4, P
minecraft.gamepedia.com/Tutorials/Basic_Logic_Gates
CS/COE0447 Computer Organization & Assembly Language
Instructor Paul Pearce
Lecturer SOE Dan Garcia
en.wikipedia.org/wiki/Conway%27s_Game_of_Life
Digital Logic.
February 7, 2002 John Wawrzynek
robosavvy.com/forum/viewtopic.php?p=32542
Boolean Algebra.
Inst.eecs.berkeley.edu/~cs61c CS61CL : Machine Structures Lecture #8 – State Elements, Combinational Logic Greet class James Tu, TA.
Lecturer PSOE Dan Garcia
TA David “The Punner” Eitan Poll
Lecturer SOE Dan Garcia
Lecturer PSOE Dan Garcia
Instructor: Michael Greenbaum
Presentation transcript:

inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 23 – Representations of Combinatorial Logic Circuits 2006-10-20 TA/Punner David Poll www.depoll.com IE7 Released Greet class This week, after more than 3 years since the last major update, Microsoft finally releases the next generation of their Internet Explorer web browser www.microsoft.com/ie

Hello “Hello, world!”

Review State elements are used to: Build memories Control the flow of information between other state elements and combinational logic D-flip-flops used to build registers Clocks tell us when D-flip-flops change Setup and Hold times important We pipeline long-delay CL for faster clock Finite State Machines extremely useful Represent states and transitions

Combinational Logic FSMs had states and transitions How to we get from one state to the next? Answer: Combinational Logic

Truth Tables

TT Example #1: 1 iff one (not both) a,b=1 y 1

TT Example #2: 2-bit adder How Many Rows?

TT Example #3: 32-bit unsigned adder How Many Rows?

TT Example #3: 3-input majority circuit

Logic Gates (1/2)

And vs. Or review – Dan’s mnemonic AND Gate C A B Symbol Definition AND

Logic Gates (2/2)

2-input gates extend to n-inputs N-input XOR is the only one which isn’t so obvious It’s simple: XOR is a 1 iff the # of 1s at its input is odd 

Truth Table  Gates (e.g., majority circ.)

Truth Table  Gates (e.g., FSM circ.) PS Input NS Output 00 1 01 10 or equivalently…

George Boole, 19th Century mathematician Boolean Algebra George Boole, 19th Century mathematician Developed a mathematical system (algebra) involving logic later known as “Boolean Algebra” Primitive functions: AND, OR and NOT The power of BA is there’s a one-to-one correspondence between circuits made up of AND, OR and NOT gates and equations in BA + means OR,• means AND, x means NOT

Boolean Algebra (e.g., for majority fun.) y = a • b + a • c + b • c y = ab + ac + bc

Boolean Algebra (e.g., for FSM) PS Input NS Output 00 1 01 10 or equivalently… y = PS1 • PS0 • INPUT

BA: Circuit & Algebraic Simplification BA also great for circuit verification Circ X = Circ Y? use BA to prove!

Laws of Boolean Algebra

Boolean Algebraic Simplification Example

Canonical forms (1/2) Sum-of-products (ORs of ANDs)

Canonical forms (2/2)

Peer Instruction (a+b)• (a+b) = b N-input gates can be thought of cascaded 2-input gates. I.e., (a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) where ∆ is one of AND, OR, XOR, NAND You can use NOR(s) with clever wiring to simulate AND, OR, & NOT ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT Answer: [correct=5, TFF] Individual (6, 3, 6, 3, 34, 37, 7, 4)% & Team (9, 4, 4, 4, 39, 34, 0, 7)% A: T [18/82 & 25/75] (The game breaks up very quickly into separate, independent games -- big win to solve separated & put together) B: F [80/20 & 86/14] (The game tree grows exponentially! A better static evaluator can make all the difference!) C: F [53/57 & 52/48] (If you're just looking for the best move, just keep theBestMove around [ala memoizing max])

Peer Instruction Answer (a+b)•(a+b) = aa+ab+ba+bb = 0+b(a+a)+b = b+b = b TRUE (next slide) You can use NOR(s) with clever wiring to simulate AND, OR, & NOT. NOR(a,a)= a+a = aa = a Using this NOT, can we make a NOR an OR? An And? TRUE (a+b)• (a+b) = b N-input gates can be thought of cascaded 2-input gates. I.e., (a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) where ∆ is one of AND, OR, XOR, NAND You can use NOR(s) with clever wiring to simulate AND, OR, & NOT ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT

Peer Instruction Answer (B)   N-input gates can be thought of cascaded 2-input gates. I.e., (a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) where ∆ is one of AND, OR, XOR, NAND…FALSE Let’s confirm! CORRECT 3-input XYZ|AND|OR|XOR|NAND 000| 0 |0 | 0 | 1 001| 0 |1 | 1 | 1 010| 0 |1 | 1 | 1 011| 0 |1 | 0 | 1 100| 0 |1 | 1 | 1 101| 0 |1 | 0 | 1 110| 0 |1 | 0 | 1 111| 1 |1 | 1 | 0      0  0   0   1      0  1   1   1     0  1   1   1      0  1   0   1      0  1   1   0      0  1   0   0      1  1   1 1 CORRECT 2-input YZ|AND|OR|XOR|NAND 00| 0 |0 | 0 | 1 01| 0 |1 | 1 | 1 10| 0 |1 | 1 | 1 11| 1 |1 | 0 | 0 Answer: [correct=5, TFF] Individual (6, 3, 6, 3, 34, 37, 7, 4)% & Team (9, 4, 4, 4, 39, 34, 0, 7)% A: T [18/82 & 25/75] (The game breaks up very quickly into separate, independent games -- big win to solve separated & put together) B: F [80/20 & 86/14] (The game tree grows exponentially! A better static evaluator can make all the difference!) C: F [53/57 & 52/48] (If you're just looking for the best move, just keep theBestMove around [ala memoizing max])

Pipeline big-delay CL for faster clock “And In conclusion…” Pipeline big-delay CL for faster clock Finite State Machines extremely useful You’ll see them again in 150, 152 & 164 Use this table and techniques we learned to transform from 1 to another