Configuration and Programming Using the USART Configuration and Programming CE-2810 Dr. Mark L. Hornick

Connection between two communicating serial devices The Tx (transmit) line of one device is connected to the Rx (receive) line of the second device Both devices have to be configured identically Same baud rate, parity, #data bits, #stop bits Tx Tx Rx Rx CS-280 Dr. Mark L. Hornick

Configuration of the USART Various I/O registers are used to Control the configuration of the USART Baud rate (bits/s) Parity (even/odd/none) Number of data bits (4-9) Framing ( 1 or 2 stop bits) Represent the status of a recent transmission or reception Frame errors Data overrun errors Tx complete Rx complete CS-280 Dr. Mark L. Hornick

Lots of registers… UCSRA – USART Control/Status Register A Mainly status flags UCSRB – USART Control/Status Register B Flags for enabling transmitting, receiving, interrupts UCSRC – USART Control/Status Register C Mode selection UBRRH, UBRRL– USART Baud Rate Registers Baud rate selection UDR– USART Data Register Does two things at once: Contains data to be transmitted, or Data that is received CE-2810 Dr. Mark L. Hornick

Duality of UDR register UDR– USART Data Register TXB and RXB I/O addresses overlap When UDR is read, the contents of the Receive Buffer (RXB) are first shifted into UDR, so that UDR contains the contents of RXB When UDR is written, the contents are shifted to the Transmit Buffer (TXB) CE-2810 Dr. Mark L. Hornick

USART Baud Rate Registers URSEL – Register select UCSRC I/O address overlaps with address of UBRRH. Set to 0 if writing this Register as UBRRH; otherwise UCSRC UBRR11:0 – Baud Rate select 12-bit register specifying the USART transmit/receive baud rate. Use the following table for calculating the value to place in these bits. BAUD is in bits/sec, fosc is the Atmega32 clock frequency. CE-2810 Dr. Mark L. Hornick

USART Control/Status Register B RXCIE – Receive complete interrupt enable Set to enable Receive Complete Interrupt. Disable to avoid conflicts with Atmon. TXCIE – Transmit complete interrupt enable Set to enable Transmit Complete Interrupt. Disable to avoid conflicts with Atmon. UDRIE – Data Register Empty interrupt enable Set to enable UDRE Interrupt. Disable to avoid conflicts with Atmon. RXEN – Receiver Enable Set to enable the USART Receiver TXEN – Transmitter Enable Set to enable the USART Transmitter CE-2810 Dr. Mark L. Hornick

USART Control/Status Register A contains status bits you read RXC – Receive complete Set when data is received in the Receive Buffer (RXB) TXC – Transmit complete Set when data in the Transmit Buffer has been completely transmitted and no new data in UDR; manually cleared by writing a 1 to this bit UDRE – Data Register Empty Set when Transmit Buffer is ready to accept new data to be transmitted FE – Frame Error Set when Data in Receive Buffer had a frame error detected DOR – Data Overrun Set when Receive Buffer is full (but unread), and new data is coming in PE – Parity Error Set when Data in Receive Buffer had a parity error detected (if parity checking was enabled) CE-2810 Dr. Mark L. Hornick

USART Control/Status Registers B and C UCSZ2, UCSZ1, UCSZ0 – Character size select Together, these set the number of data bits being transmitted or received Set these to (0:1:1) for 8 data bits; see reference manual for other settings URSEL – Register select UCSRC I/O address overlaps with address of UBRRH. Set to 1 when reading this Register as UCSRC; otherwise UBRRH UMSEL – Mode select Set to 0 for Asynchronous mode UPM1, UPM0 – Parity mode select Parity disabled (0:0), Even (1:0), Odd (1:1), Reserved (0:1) USBS– Stop bit select Set to 0 for framing using a single Stop Bit CE-2810 Dr. Mark L. Hornick

How to use the USART Set baud rate via UBRRH and UBRRL Enable Transmit and Receive via UCSRB Disable all USART interrupts via UCSRB (to avoid Atmon conflicts) Set Parity, #Data bits, #Stop bits, Async via UCSRC To Receive: Poll UDRE bit in UCSRA until set Received char in UDR Repeat To Transmit: Place character to be written in UDR Poll TXC bit in USCRA until set CS-280 Dr. Mark L. Hornick

The USART can receive while it is transmitting But the TXB and RXB buffers can each hold only one character So you must keep polling RXC to avoid dropping received characters And you must poll UDRE before sending another character to ensure that TXC has been emptied CS-280 Dr. Mark L. Hornick