Instruction encoding We’ve already seen some important aspects of processor design. A datapath contains an ALU, registers and memory. Programmers and compilers use instruction sets to issue commands. Now let’s complete our processor with a control unit that converts assembly language instructions into datapath signals. Today we’ll see how control units fit into the big picture, and how assembly instructions can be represented in a binary format. On Wednesday we’ll show all of the implementation details for our sample datapath and assembly language. 12/7/2018 Instruction encoding

Translating the C if-then statement We can use branch instructions to translate high-level conditional statements into assembly code. Sometimes it’s easier to invert the original condition. Here, we effectively changed the R1 < 0 test into R1 >= 0. R1 = *X; if (R1 < 0) R1 = -R1; R3 = R1 + R1; LD R1, (X) // R1 = *X BNN R1, L // Skip MUL if R1 is not negative LD R2,#0 SUB R1, R2, R1 // R1 = 0-R1 L ADD R3, R1, R1 // R3 = R1 + R1 12/7/2018 Instruction encoding

Translating the C for loop Here is a translation of the for loop, using a hypothetical BGT branch. R1 = 0; for (R2 = 1; R2 <= 5; R2++) R1 = R1 + R2; R3 = R1 + R1; LD R1, #0 // R1 = 0 LD R2, #1 // R2 = 1 FOR BGT R2, #5, L // Stop when R2 > 5 ADD R1, R1, R2 // R1 = R1 + R2 ADD R2, R2, #1 // R2++ JMP FOR // Go back to the loop test L ADD R3, R1, R1 // R3 = R1 + R1 12/7/2018 Instruction encoding

Summary of ISA Machine language is the interface between software and processors. High-level programs must be translated into machine language before they can be run. There are three main categories of instructions. Data manipulation operations, such as adding or shifting Data transfer operations to copy data between registers and RAM Control flow instructions to change the execution order Instruction set architectures depend highly on the host CPU’s design. Today we saw instructions that would be appropriate for our datapath from last week. On Wednesday we’ll look at some other possibilities. 12/7/2018 Instruction encoding

Review: Datapath Recall that our ALU has direct access only to the register file. RAM contents must be copied to the registers before they can be used as ALU operands. Similarly, ALU results must go through the registers before they can be stored into memory. We rely on data movement instructions to transfer data between the RAM and the register file. D data Write D address A address B address A data B data Register File WR DA AA BA Q D1 D0 S RAM ADRS DATA CS OUT MW +5V A B ALU F Z N C V FS MD S D1 D0 Q Constant MB 12/7/2018 Instruction encoding

Block diagram of a processor The control unit connects programs with the datapath. It converts program instructions into control words for the datapath, including signals WR, DA, AA, BA, MB, FS, MW, MD. It executes program instructions in the correct sequence. It generates the “constant” input for the datapath. The datapath also sends information back to the control unit. For instance, the ALU status bits V, C, N, Z can be inspected by branch instructions to alter a program’s control flow. Program Control signals Control Unit Datapath Status signals 12/7/2018 Instruction encoding

A specific instruction set The first thing we must do is agree upon an instruction set. For our example CPU let’s stick with the three-address, register-to-register instruction set architecture introduced in the last lecture. Data manipulation instructions have one destination and up to two sources, which must be either registers or constants. We include dedicated load and store instructions to transfer data to and from memory. Next week, we’ll learn about different kinds of instruction sets. 12/7/2018 Instruction encoding

From assembly to machine language Next, we must define a machine language, or a binary representation of the assembly instructions that our processor supports. Our CPU includes three types of instructions, which have different operands and will need different representations. Register format instructions require two source registers. Immediate format instructions have one source register and one constant operand. Jump and branch format instructions need one source register and one constant address. Even though there are three different instruction formats, it is best to make their binary representations as similar as possible. This will make the control unit hardware simpler. We’ll start by making all of our instructions 16 bits long. 12/7/2018 Instruction encoding

Register format An example register-format instruction: ADD R1, R2, R3 15 9 8 6 5 3 2 0 An example register-format instruction: ADD R1, R2, R3 Our binary representation for these instructions will include: A 7-bit opcode field, specifying the operation (e.g., ADD). A 3-bit destination register, DR. Two 3-bit source registers, SA and SB. 12/7/2018 Instruction encoding

Immediate format An example immediate-format instruction: 15 9 8 6 5 3 2 0 An example immediate-format instruction: ADD R1, R2, #3 Immediate-format instructions will consist of: A 7-bit instruction opcode. A 3-bit destination register, DR. A 3-bit source register, SA. A 3-bit constant operand, OP. 12/7/2018 Instruction encoding

PC-relative jumps and branches We will use PC-relative addressing for jumps and branches, where the operand specifies the number of addresses to jump or branch from the current instruction. We can assume each instruction occupies one word of memory. The operand is a signed number. It’s possible to jump or branch either “forwards” or “backwards.” Backward jumps are often used to implement loops; see some of the examples from last week. LD R1, #10 1000 LD R1, #10 LD R2, #3 1001 LD R2, #3 JMP L 1002 JMP 2 K LD R1, #20 1003 LD R1, #20 LD R2, #4 1004 LD R2, #4 L ADD R3, R3, R2 1005 ADD R3, R3, R2 ST (R1), R3 1006 ST (R1), R3 12/7/2018 Instruction encoding

Jump and branch format Two example jump and branch instructions: 15 9 8 6 5 3 2 0 Two example jump and branch instructions: BZ R3, -24 JMP 18 Jump and branch format instructions include: A 7-bit instruction opcode. A 3-bit source register SA for branch conditions. A 6-bit address field, AD, for storing jump or branch offsets. Our branch instructions support only one source register. Other types of branches can be simulated from these basic ones. 12/7/2018 Instruction encoding

The address field AD 15 9 8 6 5 3 2 0 AD is treated as a six-bit signed number, so you can branch up to 31 addresses forward (25-1), or up to 32 addresses backward (-25). The address field is split into two parts for uniformity, so the SA field occupies the same position in all three instruction formats. 12/7/2018 Instruction encoding

Instruction format uniformity Notice the similarities between the different instruction formats. The Opcode field always appears in the same position (bits 15-9). DR is in the same place for register and immediate instructions. The SA field also appears in the same position, even though this forced us to split AD into two parts for jumps and branches. Next lecture, we’ll see how this leads to a simpler control unit. 15 9 8 6 5 3 2 0 12/7/2018 Instruction encoding

Instruction formats and the datapath The instruction format and datapath are inter-related. Since register addresses (DR, SA and SB) are three bits each, this instruction set can only support eight registers. The constant operand (OP) is also three bits long. Its value will have to be sign-extended if the ALU supports wider inputs and outputs. Conversely, supporting more registers or larger constants would require us to increase the length of our machine language instructions. 15 9 8 6 5 3 2 0 12/7/2018 Instruction encoding

Organizing our instructions How can we select binary opcodes for each possible operation? In general, “similar” instructions should have similar opcodes. Again, this will lead to simpler control unit hardware. We can divide our instructions into eight different categories, each of which require similar datapath control signals. To show the similarities within categories, we’ll look at register-based ALU operations and memory write operations in detail. 12/7/2018 Instruction encoding

Register format ALU operations ADD R1, R2, R3 All register format ALU operations need the same values for the following control signals: MB = 0, because all operands come from the register file. MD = 0 and WR = 1, to save the ALU result back into a register. MW = 0 since RAM is not modified. WR 1 D Register file A B DA AA BA A B ALU G FS V C N Z 1 0 Mux B MB 0 1 Mux D MD ADRS DATA Data RAM OUT MW constant 12/7/2018 Instruction encoding

Memory write operations ST (R0), R1 All memory write operations need the same values for the following control signals: MB = 0, because the data to write comes from the register file. MD = X and WR = 0, since none of the registers are changed. MW = 1, to update RAM. WR D Register file A B DA AA BA A B ALU G FS V C N Z 1 0 Mux B MB 0 1 Mux D MD X ADRS DATA Data RAM OUT MW 1 constant 12/7/2018 Instruction encoding

Selecting opcodes Instructions in each of these categories are similar, so it would be convenient if those instructions had similar opcodes. We’ll assign opcodes so that all instructions in the same category will have the same first three opcode bits (bits 15-13 of the instruction). Next time we’ll talk about the other instruction categories shown here. 12/7/2018 Instruction encoding

ALU and shift instructions What about the rest of the opcode bits? For ALU and shift operations, let’s fill in bits 12-9 of the opcode with FS3-FS0 of the five-bit ALU function select code. For example, a register-based XOR instruction would have the opcode 0001100. The first three bits 000 indicate a register-based ALU instruction. 1100 denotes the ALU XOR function. An immediate shift left instruction would have the opcode 1011000. 101 indicates an immediate shift. 1000 denotes a shift left. 12/7/2018 Instruction encoding

Branch instructions We’ll implement branch instructions for the eight different conditions shown here. Bits 11-9 of the opcode field will indicate the type of branch. (We only need three bits to select one of eight branches, so opcode bit 12 won’t be needed.) For example, the branch if zero instruction BZ would have the opcode 110x011. The first three bits 110 indicate a branch. 011 specifies branch if zero. 12/7/2018 Instruction encoding

Sample opcodes Here are some more examples of instructions and their corresponding opcodes in our instruction set. Several opcodes have unused bits. We only need three bits to distinguish eight types of branches. There is only one kind of jump and one kind of load instruction. These unused opcodes allow for future expansion of the instruction set. For instance, we might add new instructions or new addressing modes. 12/7/2018 Instruction encoding

Sample instructions Here are complete translations of the instructions. The meaning of bits 8-0 depends on the instruction format. The colors are not supposed to blind you, but to help you distinguish between destination, source, constant and address fields. 12/7/2018 Instruction encoding

Summary Today we defined a binary machine language for the instruction set from yesterday. Different instructions have different operands and formats, but keeping the formats uniform will help simplify our hardware. We also try to assign similar opcodes to “similar” instructions. The instruction encodings and datapath are closely related. For example, our opcodes include ALU selection codes, and the number of available registers is limited by the size of each instruction. This is just one example of how to define a machine language. On Wednesday we’ll show how to build a control unit corresponding to our datapath and instruction set. This will complete our processor! 12/7/2018 Instruction encoding