Gigabit Ethernet Design ECE 4006C – Spring 2003 Group 7 Presentation #5 Courtenay Smith February 20th, 2003

Presentation #5 - February 20, 2003 Progress Report Optical Link Budget completed. VCSELs and PDs arrived. Tx/Rx schematic and layout complete. Ordering passives. Presentation #5 - February 20, 2003

Presentation #5 - February 20, 2003 First - Correction Wrong! Right! Presentation #5 - February 20, 2003

Presentation #5 - February 20, 2003 Optical Link Budget 100   Rbias  1 k ( Digikey: 3386-P-102 ) 2 k  Rmod  30 k ( Digikey: 3386-P-203 ) Presentation #5 - February 20, 2003

Presentation #5 - February 20, 2003 Tx/Rx Schematic Presentation #5 - February 20, 2003

Presentation #5 - February 20, 2003 Tx/Rx Layout Space for more conservative design…. Presentation #5 - February 20, 2003

Tx/Rx AGGRESSIVE Layout Filter Presentation #5 - February 20, 2003

Presentation #5 - February 20, 2003 Gantt Chart On Schedule Progress Still to come Event Presentation #5 - February 20, 2003

Presentation #5 - February 20, 2003 Next Week… Receive Passives. Order layouts. Continue work on midterm paper. Presentation #5 - February 20, 2003

Dan Quayle Quote of the Day.. “I was recently on a tour of Latin America, and the only regret I have was that I didn't study Latin harder in school so I could converse with those people…” Presentation #5 - February 20, 2003