LHCb PileUp VETO L0 trigger system using large FPGAs (M LHCb PileUp VETO L0 trigger system using large FPGAs (M. van Beuzekom, W. Vink, L.W. Wiggers, M. Zupan) Concept Detectors/Hybrid Overview/architecture System Specific Technical Items: Beetle Hybrid Optical Connections Prototype Board Outlook, experience, conclusions 7-12-2018 L.W. Wiggers - NIKHEF

Concept Reject event with multiple interactions (>1 or >2) at L0 to increase B-rate on tape L0 time = 4 us, L0-Veto < 2.2 us. Use of R-strip (not phi-strip) VELO detectors only SC/daq-elements common to VELO (level1 vertex locator) to simplify 7-12-2018 L.W. Wiggers - NIKHEF

Example of multiple event in VETO/VELO set-up: yellow: B-event red/orange: mb-events VETO det. Not all mb-events are that hard! 7-12-2018 L.W. Wiggers - NIKHEF

Concept-cntd Correlate hits of 2 Si R-planes in matrix: xxxxxxxx Histogram the entries Search for highest peak Mask hits from peak Search for peaks (+content) again Output results (0/1/2/more) to L0DU # peaks to ECS (SC) for Lumi 7-12-2018 L.W. Wiggers - NIKHEF

Concept-cntd The closer to detectors: better z-resolution more background combinations variable binning Combine hits of left/right halves: 1.5 cm displaced in z Balance purity/efficiency of vertex finding: 95% eff. for B-events and 20% retention of multiple mb-events (gain of 30% in B-events at 1 MHz L0-rate) 7-12-2018 L.W. Wiggers - NIKHEF

Overview System Buffering of detector signals (Beetle-comparator output) at Repeater Station on tank (if needed): rad-hard LVDS drivers! VETO system behind wall Use of optical links (identical to Mu-L0) Use of VELO electronics for HV etc. 7-12-2018 L.W. Wiggers - NIKHEF

Overview System (cntd) Avoid radiation damage and SEU/SEL etc.! # spares; easy acces Avoid situation: “NASA looking for old parts (Intel 8086’s) to keep space shuttles aloft”- May 2002 7-12-2018 L.W. Wiggers - NIKHEF

Beetle 1.2 Comparator output per 4 channels (128 ch. inputs in total): fast pulse to prevent overspill (reflection of previous event) Binary or analog pipeline data Radiation hard up to 40 Mrad Version 1.2 available this summer: new front-end and improved comparator 7-12-2018 L.W. Wiggers - NIKHEF

Hybrid 16 Beetle chips: 64 analog pairs + 256 LVDS comparator pairs # channels depend on detector design (under discussion): 8-16 Beetle chips per hybrid = 512 – 1024 system channels in total 8-layer design in production at CERN Beetle-VELO hybrid (+detector) produced at NIKHEF 7-12-2018 L.W. Wiggers - NIKHEF

Hybrid (detail) Many lines to output digital comparator info: 50 um traces/spacing 300 um (micro)vias MentorGraphics software did not like rotating 7-12-2018 L.W. Wiggers - NIKHEF

Optical Connections CMS GOL chip TLK2501 (16-bit, 80 MHz) serializer chip Agilent transceiver 12-channel ribbon Timing: pipelining should be maintained! Synchronization with LHCb valid pulse 7-12-2018 L.W. Wiggers - NIKHEF

Architecture VETO system Multiplexed output to Vertex Boards (2-4 boards) Vertex Boards (4 boards + 1 as spare and for checks): one Vertex Finder per event Output to global trigger (1 board) 7-12-2018 L.W. Wiggers - NIKHEF

Choice for Xilinx FPGA XCV3200E as processing element: 0.18 um 6-Layer Metal Process 4.074.387 System Gates 804 I/O pins (344 diff LVDS pairs) 1156 pin BGA (challenge!) But: first difficult to get samples; 5000 euro 7-12-2018 L.W. Wiggers - NIKHEF

Vertex Prototype Processor Board 6U board, full speed Processing in 2 FPGAs (70 % utilization, 40 MHz): 48 steps x 25 ns = 1.2 us Long synthesis + fitting steps (LeonardoSpectrum) JTAG connection 12-layer PCB, complicated routing 7-12-2018 L.W. Wiggers - NIKHEF

Prototype VFB Board 7-12-2018 L.W. Wiggers - NIKHEF

Test board VME interface Loading patterns Output of results Xilinx XCV1600E (2 Mgates) 7-12-2018 L.W. Wiggers - NIKHEF

Internal system connections 9U/40 cm boards: 1 crate PCI-connectors for point-to-point data connections (80 MBit lines) VME for loading/monitoring 7-12-2018 L.W. Wiggers - NIKHEF

Backplane/ connectors 700-800 output pins/9U board + VME P1 and P2 All PCI backplane: up to 1400 signal pins per board for 8+2 row connectors Study to increase data transfer frequency to 160 Mbit/s: less pins 7-12-2018 L.W. Wiggers - NIKHEF e.g.: all PCI backplane

Experience Routing of board with large FPGAs time-consuming Synthesis + fitting steps FPGA take long (now about one day) Ball Grid Array: use of dummies to prevent failing connections Testability of code in FPGA important (output of intermediate results) Internal system connectivity somewhat problematic 7-12-2018 L.W. Wiggers - NIKHEF

Outlook Combining other functions in even larger FPGA (refining algorithm: effect of left/right displacements) Test of processor board; provide more testing facilities; design monitoring facilities Study effects of increase of internal/output frequencies 7-12-2018 L.W. Wiggers - NIKHEF

Conclusions Use of Si strip detector data for trigger purposes at the very first trigger level (LHCb-L0) Simple algorithm for determining vertex positions, also for use in Luminosity Monitoring Flexibility by applying FPGA as processor element 7-12-2018 L.W. Wiggers - NIKHEF