JAZiO Incorporated 1 Change No-Change Concept

JAZiO Incorporated 2 Change /No Change Concept Comp A Data In VTR Data In Comp A No Change This band is based on process mismatch (device W, L, etc.), reflection or overshoot (discontinuity, termination, inductance, etc.). 3 Case 3: Comp A remains High (weakly) while the Data Output retains the previous data Case 1: Comp A amplifies the change and the data passes through the Steering Logic Change 1 The time gap is used by the steering logic to pass the change or block the no-change from reaching the data output 1 THE GAP 1

JAZiO Incorporated 3 JAZiO bus is usually a terminated uniform transmission line (resistive characteristic) Differential amplifiers in the JAZiO receiver after the input protection resistance receive exponential signals (low pass filter characteristic) Tune the receiver load capacitance and input protection resistance to get desired signal and VTR slew characteristics and the change/no-change gap JAZiOs Transition Detection JAZiO receiver rejects undesired high frequency noise by doing transition detection instead of conventional peak detection!

JAZiO Incorporated 4 Note: Red area is insufficient differential for either change or no change detection; Green indicates GAP region. VTR S0 S1 S3 VTR and Signal Relationship (same levels and similar rise/fall times on VTRs versus signals) Change Early in time Quick amplification (after signal and VTR crossing) 2X the conventional signal Steering Logic Later in time (delayed from VTR/VTR crossing) Time 85 to 95% of the same bit-time Xor low crossing No Change Much later in time (after VTR and signal become equal) Slow amplification (noise and device mismatch)

JAZiO Incorporated 5 Note: Red area is insufficient differential for either change or no change detection; Green indicates GAP region (no change can never occur). VTR S0 S1 S3 VTR and Signal Relationship (same levels and different rise/fall times on VTRs versus signals) Change Earlier in time Quick amplification (after signal and VTR crossing) 2X the conventional signal Steering Logic Later in time (delayed from VTR/VTR crossing) Time 100 to 110% of the same bit-time Xor low crossing No Change Much later in time (cannot be in the same bit-time) Requires large noise and/or device mismatch

JAZiO Incorporated 6 Note: Red area is insufficient differential for either change or no change detection; Green indicates GAP region (no change can never occur). VTR S0 S1 S3 VTR to Signal Techniques VTR and Signal Relationship (same rise/fall times but different levels on VTRs versus signals) Change Earlier in time Quick amplification (after signal and VTR crossing) 2X the conventional signal Steering Logic Later in time (delayed from VTR/VTR crossing) Time 110 to 120% of the same bit-time Xor mid-point crossing No Change Will not occur (100mV noise margin between signal and VTR) Requires large noise and/or device mismatch

JAZiO Incorporated 7 Bit to Bit Static De-Skew Data Input 0 Bits 1-7 VTR SL VTR Data Output 0 SIGNALS FROM PADS Data Input 8 Data Input 9 Data Input 17 Data Output 8Data Output 9 Data Output 17 Bits XOR Static De-skew XOR Static De-skew XOR Static De-skew XOR Static De-skew XOR Static De-skew XOR Static De-skew XOR Static De-skew XOR Static De-skew

JAZiO Incorporated 8 Current Switching Technologies Change determines voltage and timing margins –Higher voltage swings increase power and noise –Slower rise/fall times reduce the set-up and hold time margins or frequency Receiver Change Margin JAZiO Switching Change is made much easier –Self timed (increased timing margins) –Larger signal (~2x) –Less noise (lower slew rate and common mode) –Low power (smaller swings, edge current, and lower termination voltage) –No set-up and hold time requirement at the pin

JAZiO Incorporated 9 1.Diff-Amp biasing 2.Diff-Amp gain 3.Slew rate of signals and VTR at the receiver 4.Timing skew : VTRs to signals 5.Voltage skew : VTRs to signals JAZiO No-Change Margin Optimize the change/no-change gap based on highest operating frequency!

JAZiO Incorporated 10 DRAM Single Channel Example

JAZiO Incorporated 11 Clock Source Upper Address & Control Lines Lower Data Lines VTR0 VTR1 Lower Address & Control Lines 5 Bit Addr & Ctrl VTR0 & VTR0 Data VTR1 & VTR1 Data Upper Data Lines VTT CONTROLLERCONTROLLER DRAM Clock

JAZiO Incorporated 12 Read Cycle 8-Bit Burst

JAZiO Incorporated 13 Write Cycle 8-Bit Burst

JAZiO Incorporated 14 Read, Read,Write, Read Burst VTR0 VTR1 CS/RAS CAS/WE ADR 0:7/ ADR 8:15 I/O 0:17 10 Cycles CLK

JAZiO Incorporated 15 Data Latch Timing (4-bit burst) SL SLL0 SLL1 SLL2 SLL3 SLD2 SL SLD2 Receiver Enable Reset FF Divide By 2 SL SLL1 SLD2 SL SLL2 SLD2 SL SLL3 SLD2 SL SLL0 SLD2

JAZiO Incorporated 16 D0 SLL0 SLL1 SLL2 SLL3 SLL2 SLL3 1.5 to 2.0ns delay 1.0 to 1.5ns delay 0.5 to 1.0ns delay D17 1 to 4 Serial to Parallel Data Latch D3 D71 D0 D1 D2

JAZiO Incorporated 17 DRAM Dual Channel Example (skew between different DRAMs)

JAZiO Incorporated 18 Data 0:8 Lower Address & Control Lines Data 9:17 VTR0 Clock Source VTT VTR1 VTT CONTROLLERCONTROLLER DRAM VTR2 Data VTR2 & VTR2 Data VTT 5 Bit Addr & Ctrl VTR0 & VTR0 Data VTR1 & VTR1 Data DRAM Data 18:26 Data 27:35 VTT 5 Bit Addr & Ctrl Clock VTT Clock Upper Address & Control Lines

JAZiO Incorporated 19 Data Flow From DRAM To Controller VTT CLK VTT Data & VTR2s Receiver & Termination Latch Level Converter Vernier JAZiO DRAM Level Converter Vernier JAZiO Latch CORE DRAM Level Converter Vernier JAZiO Latch CORE DRAM Level Converter Vernier JAZiO Latch CORE DRAM Level Converter Vernier JAZiO Latch CORE DRAM Level Converter Vernier JAZiO Latch CORE DRAM Level Converter Vernier JAZiO Latch CORE JAZiO 1 to 4 Parallel Latch 1 to 4 Parallel CONTROLLER Data & VTR1s

JAZiO Incorporated 20 DRAM to DRAM Skew Dual Channel Data Latching Window SL VTR2 SLL0 SLL1 SLL2 SLL3 CLK SL VTR1 SLL0 SLL1 SLL2 SLL3 TOPTOP BOTTOMBOTTOM

JAZiO Incorporated 21 Design Optimization

JAZiO Incorporated 22 Design Optimization Step 1 Design DC bias point of the differential amplifier to be approximately (Voh+Vol)/2 (with typical conditions) with a gain of 3 to 4 Step 2 Line up SL and SL to cross at the mid-point and look symmetrical to one other (with typical conditions) Step 3 Design the XORs to have no glitches and to cross low with 200pS skew in the external Data Input (with typical conditions). Step 4 Design the output driver for slow turn-on and turn-off, to get symmetric rise and fall times and a transition time equal to 80% of the data rate (with typical conditions) up to a max of 2nS.

JAZiO Incorporated 23 Diff-Amp Optimization VTR Data Input Output Under Typical Conditions VTR = Data Input = (Vih+Vil)/2 Data Output = ½ Vcc VTR = Data Input = Vih Data Output < (½Vcc-200mV) VTR = Data Input = Vil Data Output > (½Vcc+200mV)

JAZiO Incorporated 24 Data Output XOR-A SL XOR-B SL The XORs should act like a low-pass filter (slow path) First stage nand gates bias point should be approximately mid-point Second stage nand gate bias point should be 1/3 to 1/4 VCC Data Output

JAZiO Incorporated 25 JAZiO Scalability 1.Voltage Works with lower voltage as the technology shrinks 2.Frequency Works at higher frequency as the logic speeds up 3.Power Reduces speed-power-product at higher frequency and lower power supply 4.Bus Size Works from point-to-point to large DRAM buses 5.Bus Width Uses multiple VTRs for wider buses (x32, x64, etc.) 6.Timing Margins Transition time / cycle time ratio does not reduce