1 Dynamic Interconnection Networks Buses CEG 4131 Computer Architecture III Miodrag Bolic

2 Overview Basic theory on buses –Arbitration –High performance bus protocols Avalon bus

3 Big Picture Interconnection Networks MM MM PPPPP Focus of this lecture

4 Interconnection Network Static Dynamic Bus-basedSwitch-based 1-D2-DHC SingleMultiple SSMS Crossbar Interconnection Network Taxonomy [5]

5 Addressing and Timing [2] Bus Addressing Broadcast: –write involving multiple slaves Synchronous Timing: –All bus transaction steps take place at a fixed clock edges –simple to control –suitable for connecting devices having relatively the same speed Asynchronous Timing: –based on a handshaking –offers better flexibility via allowing fast and slow devices to be connected in the same bus. Typical time sequence when information is transferred from the master to slave.

6 Bus arbitration Bus arbitration scheme: –A bus master wanting to use the bus asserts the bus request –A bus master cannot use the bus until its request is granted –A bus master must signal to the arbiter the end of the bus utilization Bus arbitration schemes usually try to balance two factors: –Bus priority: the highest priority device should be serviced first –Fairness: Even the lowest priority device should be allowed to access the bus Bus arbitration schemes can be divided into several broad classes: –Daisy chain arbitration (not used nowadays) –Arbitration with the independent request and grant –Distributed arbitration

7 Independent Request and Grant [1] Multiple bus-request and bus- grant signal lines are provided for each master Any priority-based or fairness based bus allocation can be used. Advantages –flexibility –faster arbitration time Disadvantages: –large number of arbitration lines

8 Bus allocation techniques [1] Round-robin –The request that was just served should have the lowest priority on the next round TDMA –Fixed allocation of the slot to the master Unequal-priority protocol –Each processor is assigned a unique priority. –Additional procedures are required to establish fairness

9 Bus Pipelining [1] Several cycles are needed to read or write one data Since the bus is not used in all cycles, pipelining can be used to increase the performance AR – Arbitration request, ARB cycle for processing inside the arbiter, AG – Grant signal is set RQ – request signal is set P- pause RPLY – reply from the memory or I/O

10 Bus Pipelining [1]

11 Split Transactions [1] In a split-transaction bus a transaction is divided into a two transactions –request-transaction –reply-transaction Both transactions have to compete for the bus by arbitration

12 Split Transactions [1]

13 Burst Messages [1]

14 Avalon Bus Proprietary bus specification used with Nios II Principal design goals of the Avalon Bus –Address Decoding –Data-Path Multiplexing –Wait-State Insertion –Arbitration for Multi-Master Systems Transfer Types –Slave Transfers –Master Transfers –Pipelined Transfers –Burst transfers 32-Bit Nios Processor Switch PIO LED PIO 7-Segment LED PIO PIO-32 User- Defined Interface ROM (with Monitor) UARTTimer Address (32) Read Write Data In (32) Data Out (32) IRQ IRQ #(6) Avalon Bus Nios Processor

15 Direct Memory Access (DMA) –Processor Waits For Bus During DMA System CPU (Master 1) DMA Arbitor 100Base-T (Master 2) System Bus I/O 1 I/O 2 Data Memory DMA Bus Arbiter Bottleneck Arbiter Determines Which Master Has Access To Shared Bus Program Memory Masters Slaves Traditional Multi-Masters Control direction

16 Master 1 (Nios CPU) I/O 1 Program Memory Arbiter Data Memory 1 Master 2 (100Base-T) ID I/O 2 Avalon Bus Uses Fairness Arbitration Masters Slaves Simultaneous Multi-Master Bus Control direction

17 Master Arbitration Scheme Nios Multi-Master Avalon Bus utilizes Fairness arbitration scheme –Each Master/Slave pair is assign an integer shares –Upon conflict Master with most shares takes bus until all shares are used –Master with least shares then takes bus until all shares are used –Assuming all Masters continuously request the bus, they will each be granted the bus for a percentage of time equal to the percentage of total master shares that they own

18 Set Arbitration Priority View => Show Arbitration Priorities

19 Address Decoding [4]

20 Data-Path Multiplexing [4]

21 Master Read Transfer [3] Assert addr, be, read Wait for waitrequest = 0 Read in Data End of transfer

22 Master Write Transfer [3] Assert addr, be, read Assert Write Data Wait for waitrequest = 0 End of transfer

23 Slave Read Transfer [3] 0 Setup Cycles 0 Wait Cycles

24 Slave Read Transfer [3] 1 Setup Cycle 1 Wait Cycle

25 Slave Write Transfer [3] 0 Setup Cycles 0 Wait Cycles 0 Hold Cycles

26 Slave Write Transfer [3] 1 Setup Cycle 0 Wait Cycles 1 Hold Cycle

27 References 1.W. Dally, B. Towles, Principles And Practices Of Interconnection Networks, Morgan Kauffman, K. Hwang, Advanced Computer Architecture Parallelism, Scalability, Programmability, McGraw-Hill Altera Corp., Avalon Interface Specification, Altera Corp., Quartus II Handbook, Volume 4, H. El-Rewini and M. Abd-El-Barr, Advanced Computer Architecture and Parallel Processing, John Wiley and Sons, 2005.