CS 140 Lecture 16 Professor CK Cheng 11/21/02

System Designs Introduction Spec Implementation

Register D LD CLK CLR Q Q (t+1) = (0, 0, .. , 0) if CLR = 1 = D if LD = 1 and CLR = 0 = Q (t)’ if LD = 0 and CLR = 0

I. Introduction 64 Data Subsystems 64 Data Inputs Data Outputs Control Signals Conditions Control Subsystems Control Outputs Control Inputs go done (ready)

Components Storage Modules Operators Interconnections Sequential machines Functions Data storage Data transformation Control of data transfers Control of transformations Control of the sequential system Data Subsystem Control

Array of Registers: Sharing connections and controls RAM FIFO LIFO D Storage Modules Registers: If c then R  0 c LD R Array of Registers: Sharing connections and controls RAM FIFO LIFO D Decoder address c R

RAM Size of RAM larger than registers Decoder Address FIFO (First in first out) LIFO (Like a stack)

Functional Modules A B CASE Op-Sel Is When F1 => Z <= A op1 B . End CASE Operation selection Z Interconnections (Wire & Switches) 1. Single line (shifting, time sharing)

2. Band of Wires (BUS) 3. Shared Bus ….. R1 R2 R3 Rm x x c c d DEMUX MUX 1 2 3 .. N 1 2 3 .. N y y

4. Crossbar (Multiple buses running horizontally) m buses 64 m simultaneous transfers are possible Very expensive. MUX MUX MUX …

Program: Objects (Registers, Outputs of combinational logic) Operation Assignment Sequencing Example: Signal R1, R2, Bit Vector V (15 down to 0); Z  A + B ( A, B, Z need to be defined) R1  R2 Begin End if ( ) then ( ), ENDIF;

S1 Ex. If C then R1 S1 Else R2  S2 Endif; R1 C S2 R2 LD C S2 R2 If C1 then X  A Else X  B + C Endif If C2 then G  X A B C Adder 1 0 MUX C1 C2 G CLK