MIL/STD-1553B Bus Overview J. Frederick Bartlett Fermilab June 3, 1999.

Slides:

Advertisements

Similar presentations

RS232 and RS485 Fundamental.

Advertisements

1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 4 Computing Platforms.

XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing.

XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 22 October 2009 Martin Postranecky, Matt Warren, Matthew Wing.

By Sunil G. Kulkarni, SO/F, Pelletron-Linac Facility, BARC-TIFR. 21/01/2011 ASET.

Generic Remote Interface Unit (RIU) Interface Control Document (ICD) CCSDS SOIS 2013 spring meeting Glenn Rakow/NASA-GSFC.

Computer Architecture and Organization

MIL-STD-1553 David Koppel Excalibur Systems.

Chapter 8 Interfacing Processors and Peripherals.

150 E. Arrow Hwy. San Dimas, CA

6-April 06 by Nathan Chien. PCI System Block Diagram.

Processor Data Path and Control Diana Palsetia UPenn

Chapter 7: System Buses Dr Mohamed Menacer Taibah University

Copyright © 2010 Agilent Technologies Characterizing the Physical Layer of MIL-STD 1553 Differential Bus Networks Presented by: Johnnie Hancock Agilent.

Computer Architecture

Digital Computer Fundamentals

SynApps love, vme, ebrick modules EPICS Collaboration Meeting – Beamline Controls SIG Workshop David Kline June 12–16, 2006.

Autonomous Tracking Unit John Berglund Randy Cuaycong Wesley Day Andrew Fikes Kamran Shah Professor: Dr. Rabi Mahapatra CPSC Spring 1999 Autonomous.

Gursharan Singh Tatla PIN DIAGRAM OF 8086 Gursharan Singh Tatla Gursharan Singh Tatla

Press any key to continue by Marc Ruocco 1 High-Speed Interfaces: FPDP and RACEway RACE, RACEway and RACE++ are trademarks of Mercury Computer Systems,

Dirk Zimoch, EPICS Collaboration Meeting, Vancouver 2009 Real-Time Data Transfer using the Timing System (Original slides and driver code by Babak Kalantari)

DriveAP 1.2 & 2.1 DriveWare®.

1 SWE Introduction to Software Engineering Lecture 21 – Architectural Design (Chapter 13)

Tracker Controls MICE Controls and Monitoring Workshop September 25, 2005 A. Bross.

Midterm Tuesday October 23 Covers Chapters 3 through 6 - Buses, Clocks, Timing, Edge Triggering, Level Triggering - Cache Memory Systems - Internal Memory.

CSS Lecture 2 Chapter 3 – Connecting Computer Components with Buses Bus Structures Synchronous, Asynchronous Typical Bus Signals Two level, Tri-state,

OPC Overview OPC Device Support (PLC Gateway for 3.14) Ralph Lange – EPICS Collaboration Meeting at SLAC, April 2005.

14 Nov 2000G3/FlexIO/PLC5/VSIOD8 Carl Lionberger 1 EPICS Support for G3/FlexIO/PLC5/VSIOD8 Carl Lionberger Group3™ optical-fiber-connected I/O AB FlexIO™

Dirk Zimoch, EPICS Meeting April 2007, Hamburg Siemens S7 PLC Communication.

Managed by UT-Battelle for the Department of Energy Kay Kasemir Sept EPICS EtherIP Driver.

Argonne National Laboratory is managed by The University of Chicago for the U.S. Department of Energy P0 Feedback Project: Merging EPICS with FPGA’s Nicholas.

D.H.S. Digijock Home Security ECE477 – Team 7 Linda Stefanutti Zach Smith Stuart Pulliam Will Granger Software Design Narrative.

A U.S. Department of Energy Office of Science Laboratory Operated by The University of Chicago Argonne National Laboratory Office of Science U.S. Department.

SOIS P&P Concepts & Mapping of the Device Discovery service onto the MIL-STD-1553 Massimiliano Ciccone ESA/ESTEC 02-Oct-2007 (CCSDS-Darmstadt)

8254 Programmable Interval Timer

APS BPM and power supply applications on micro-IOCs W. Eric Norum

Writing Your Own Custom IP Drivers for the IOC Blade 9010 By Darrell Nineham 5 Craddock.

8 May 2001EPICS Group3 Carl Lionberger1 EPICS Support for Group3 Control System Carl Lionberger Group3™ optical-fiber-connected I/O Software and operational.

AT91 Embedded Peripherals

EPICS devSNMP Extensions Euan Troup, CSIRO Australia Telescope National Facility ASKAP Project Paul Wild Observatory.

Ralph Lange: OPC Gateway (Device Support) OPC Gateway (Device Support) Ralph Lange – EPICS Collaboration Meeting March SSRF.

How to count PMT pulses Victor Kornilov Sternberg astronomical institute I count photons 25 years.

Berliner Elektronenspeicherringgesellschaft für Synchrotronstrahlung mbH (BESSY) OPC - Device Support Bernhard Kuner, Carsten Winkler BESSY, Berlin, Germany.

A U.S. Department of Energy Office of Science Laboratory Operated by The University of Chicago Argonne National Laboratory Office of Science U.S. Department.

A U.S. Department of Energy Office of Science Laboratory Operated by The University of Chicago Argonne National Laboratory Office of Science U.S. Department.

The Local Christopher Perez Justin Pun Jonathan Varsanik.

More Digital circuits. Ripple Counter The most common counter The problem is that, because more than one output is changing at once, the signal is glichy.

Input/Output Computer component : Input/Output I/O Modules External Devices I/O Modules Function and Structure I/O Operation Techniques I/O Channels and.

Experience Running Embedded EPICS on NI CompactRIO Eric Björklund Dolores Baros Scott Baily.

NSBE Seminar1 MIL-STD 1553 on the International Space Station’s Command and Data Handling System NSBE training seminar September 25, 2003 P.Eugene Jackson.

Fast Fault Finder A Machine Protection Component.

Block Diagram MTB Board #1 PC LabVIEW Program #1 Config File #1 MTB Board #2 LabVIEW Program #2 Config File #2 Database SUB record for each channel. Other.

Control System Overview J. Frederick Bartlett Fermilab June 1,1999.

Connecting EPICS with Easily Reconfigurable I/O Hardware EPICS Collaboration Meeting Fall 2011.

A 3-D Rendering System Final Project Ben Hebert & Mayur Desai Spring 2005.

Motor drivers for asyn motor device support Mark Rivers GeoSoilEnviroCARS, Advanced Photon Source University of Chicago.

New IP Drivers using drvIpac Module Driver:CANopen Carrier Driver:GPFC drvIpac ?? CANopen Tip810 CAN Tip810 mv162GPFCatc40vipc310vipc616 Module driver.

1 1999/Ph 514: Supported Hardware EPICS Supported Hardware Ned D. Arnold APS.

Babak Kalantari, EPICS Collaboration Meeting, Kobe 2009 A generic driver for Data Buffer of MRF Timing System Babak Kalantari Paul Scherrer Institute Switzerland.

EPICS Records J. Frederick Bartlett Fermilab June 1,1999.

ECE 456 Computer Architecture Lecture #9 – Input/Output Instructor: Dr. Honggang Wang Fall 2013.

Control System Overview J. Frederick Bartlett Fermilab June 1,1999.

1.3 The ZigBee application framework Jae Shin Lee.

GPL Board Pattern Generator for the Level-0 Decision Unit Hervé Chanal, Rémi Cornat, Emmanuel Delage, Olivier Deschamps, Julien Laubser, Jacques Lecoq,

PLC 5 I/O Addressing.

asyn Driver Tutorial Measurement Computing 1608GX-2A0

IV. Convolutional Codes

Sequential Design Example

regDev Simple access to register based devices

Presentation transcript:

MIL/STD-1553B Bus Overview J. Frederick Bartlett Fermilab June 3, 1999

Online WorkshopJune 3, 1999 MIL/STD 1553 Field Bus Support The MIL/STD-1553B standard 1 MHz clock Manchester II bi-phase code Transformer coupling Bus lengths 100 meters+ 16-bit word size 20 μ sec/word Status word for each transaction High noise rejection Very Robust

Online WorkshopJune 3, 1999 MIL/STD 1553 Field Bus Properties Addressing structure Remote terminal (RT) - 31 Broadcast (all RTs) Subaddress - 30 Word count - 1 to 32 Mode function

Online WorkshopJune 3, 1999 VxWorks/EPICS 1553 Support VxWorks Driver Uses a POSIX queue for serialization Multiple transactions per queue element (atomic) User callback function Long data blocks sequenced as multiple transactions by the driver EPICS driver wrapper

Online WorkshopJune 3, 1999 VxWorks/EPICS 1553 Support Generic record (mil1553) No device module Generic device (planned) AI, AO, BI, BO, LONGIN, LONGOUT, MBBI, MBBO, WF Rack monitor Complex record example 1U rack profile 64 A/D channels Read with two 1553 transactions 8 D/A channels 4 binary channels Input/output selection 32 word per channel