© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Bus-Based Computer Systems zBusses. zMemory devices. zI/O devices: yserial links ytimers and counters ykeyboards ydisplays yanalog I/O

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. The CPU bus zBus allows CPU, memory, devices to communicate. yShared communication medium. zA bus is: yA set of wires. yA communications protocol.

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Bus protocols zBus protocol determines how devices communicate. zDevices on the bus go through sequences of states. yProtocols are specified by state machines, one state machine per actor in the protocol. zMay contain asynchronous logic behavior.

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Four-cycle handshake device 1device 2 enq ack time device 1 device

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Four-cycle handshake, contd. 1.Device 1 raises enq. 2.Device 2 responds with ack. 3.Device 2 lowers ack once it has finished. 4.Device 1 lowers enq.

Microprocessor busses zClock provides synchronization. zR/W is true when reading (R/W is false when reading). zAddress is a-bit bundle of address lines. zData is n-bit bundle of data lines. zData ready signals when n-bit data is ready. © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed.

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Timing diagrams

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Bus read

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. State diagrams for bus read CPU device Get data Done Adrs Wait See ack Send data Release ack Adrs Wait Ack start

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Bus wait state

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Bus burst read

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Bus multiplexing CPU adrs device data adrs data enable Adrs enable

DMA zDirect memory access (DMA) performs data transfers without executing instructions. yCPU sets up transfer. yDMA engine fetches, writes. zDMA controller is a separate unit. © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed.

Bus mastership zBy default, CPU is bus master and initiates transfers. zDMA must become bus master to perform its work. yCPU cant use bus while DMA operates. zBus mastership protocol: yBus request. yBus grant. © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed.

DMA operation zCPU sets DMA registers for start address, length. zDMA status register controls the unit. zOnce DMA is bus master, it transfers automatically. yMay run continuously until complete. yMay use every n th bus cycle. © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed.

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Bus transfer sequence diagram

System bus configurations zMultiple busses allow parallelism: ySlow devices on one bus. yFast devices on separate bus. zA bridge connects two busses. © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. CPUslow device memory high-speed device bridge slow device

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Bridge state diagram

ARM AMBA bus zTwo varieties: yAHB is high-performance. yAPB is lower-speed, lower cost. zAHB supports pipelining, burst transfers, split transactions, multiple bus masters. zAll devices are slaves on APB. © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed.

Memory components zSeveral different types of memory: yDRAM. ySRAM. yFlash. zEach type of memory comes in varying: yCapacities. yWidths. © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed.

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Random-access memory zDynamic RAM is dense, requires refresh. ySynchronous DRAM is dominant type. ySDRAM uses clock to improve performance, pipeline memory accesses. zStatic RAM is faster, less dense, consumes more power.

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. SDRAM operation

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Read-only memory zROM may be programmed at factory. zFlash is dominant form of field- programmable ROM. yElectrically erasable, must be block erased. yRandom access, but write/erase is much slower than read. yNOR flash is more flexible. yNAND flash is more dense.

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Timers and counters zVery similar: ya timer is incremented by a periodic signal; ya counter is incremented by an asynchronous, occasional signal. zRollover causes interrupt.

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Watchdog timer zWatchdog timer is periodically reset by system timer. zIf watchdog is not reset, it generates an interrupt to reset the host. host CPU watchdog timer interrupt reset

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Switch debouncing zA switch must be debounced to multiple contacts caused by eliminate mechanical bouncing:

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Encoded keyboard zAn array of switches is read by an encoder. zN-key rollover remembers multiple key depressions. row

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. LED zMust use resistor to limit current:

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. 7-segment LCD display zMay use parallel or multiplexed input.

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Types of high-resolution display zLiquid crystal display (LCD) is dominant form. zPlasma, OLED, etc. zFrame buffer holds current display contents. yWritten by processor. yRead by video.

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Touchscreen zIncludes input and output device. zInput device is a two-dimensional voltmeter:

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Touchscreen position sensing ADC voltage

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Digital-to-analog conversion zUse resistor tree: R 2R 4R 8R bnbn b n-1 b n-2 b n-3 V out

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Flash A/D conversion zN-bit result requires 2 n comparators: encoder V in...

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Dual-slope conversion zUse counter to time required to charge/discharge capacitor. zCharging, then discharging eliminates non-linearities. V in timer

© 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Sample-and-hold zSamples data: converter V in