COMPUTER SYSTEMS An Integrated Approach to Architecture and Operating Systems Chapter 10 Input/Output and Stable Storage ©Copyright 2008 Umakishore Ramachandran and William D. Leahy Jr.

10.1 Communication between the CPU and the I/O devices Device Controller Input/Output Device Computer

Device controller

Memory Mapped I/O CPU Main memory Address Data Data register (address = 5000) Ready 07 IFIE… 07 Keyboard controller Status register (address = 5002)

10.2 Programmed I/O

10.3 DMA Command DMA controller Buffer256 bytes Status Device addressMemory buffer address Count Memory Memory bus CPU Go

10.4 Buses System Bus (or Memory Bus) is key resource in entire design. Functionally, bus has following components: – Address lines – Data lines – Command lines – Interrupt lines – Interrupt acknowledge lines – Bus arbitration lines

10.4 Buses Memory System bus CPU PCI bus Controller Bridge Controller

10.5 I/O Processor Shared Memory System bus CPU I/O bus Controller I/O processor Controller Bridge

10.6 Device Driver

An Example CommandController Action pan(± ɵ )Pan the camera view by ± ɵ tilt(± ɵ )Tilt camera position by ± ɵ zoom(±z)Zoom camera focus by ±z StartStart camera StopStop camera memory buffer(M) Set memory buffer address for data transfer to M number of frames (N) Set number of frames to be captured and transferred to memory to N enable interruptEnable interrupt from the device disable interrupt Disable interrupt from the device start DMAStart DMA data transfer from camera

An Example // device driver: camera // The device driver performs several functions: //control_camera_position; //convey_DMA_parameters; //start/stop data transfer; //interrupt_handler; //error handling and reporting; // Control camera position camera_position_control (angle pan_angle; angle tilt_angle; int z) { pan(pan_angle); tilt(tilt_angle); zoom(z); } // Set up DMA parameters for data transfer camera_DMA_parameters(address mem_buffer;int num_frames) { memory_buffer(mem_buffer); capture_frames(num_frames); }

An Example // Start DMA transfer camera_start_data_transfer() { start_camera(); start_DMA(); } // Stop DMA transfer camera_stop_data_transfer() { // automatically aborts data transfer // if camera is stopped; stop_camera(); } // Enable interrupts from the device camera_enable_interrupt() { enable_interrupt(); } // Disable interrupts from the device camera_disable_interrupt() { disable_interrupt(); }

An Example // Device interrupt handler camera_interrupt_handler() { // This will be coded similar to any // interrupt handler we have seen in // chapter 4. // // The upshot of interrupt handling may // to deliver events to the upper layers // of the system software (see Figure 10.9) // which may be one of the following: //- normal I/O request completion //- device errors for the I/O request // }

10.7 Peripheral Devices DeviceInput/outputHuman in the loop Data rate (circa 2008) PIODMA KeyboardInputYes5-10 bytes/secX MouseInputYes bytes/secX Graphics displayOutputNo MB/secX Disk (hard drive)Input/OutputNo MB/secX Network (LAN)Input/OutputNo1 Gbit/secX ModemInput/OutputNo1-8 Mbit/secX Inkjet printerOutputNo20-40 KB/secXX Laser printerOutputNo KB/secX Voice (microphone/speaker) Input/OutputYes10 bytes/secX Audio (music)OutputNo4-500 KB/secX Flash memoryInput/OutputNo10-50 MB/secX CD-RWInput/OutputNo10-20 MB/secX DVD-RInputNo10-20 MB/secX

10.8 Disk Storage Head Assembly All heads move together Platter Sector Top and bottom Surfaces Head Spindle Track Shaft Arm

10.8 Disk Storage Cylinder X: Track X from all 12 surfaces (2 per platter) Each circle represents two tracks: one for top surface and one for bottom surface

10.8 Disk Storage (a) Normal (Non zoned) recording(b) Zoned recording

Saga of Disk Technology Disk recording: (a) Longitudinal recording; (b) PMR

10.9 Disk Scheduling Algorithms NameNotationUnitsDescription Throughputn/TJobs/secSystem-centric metric quantifying the number of I/O requests n executed in time interval T Avg. Turnaround time (t avg ) (t 1 +t 2 +…+t n )/nSecondsSystem-centric metric quantifying the average time it takes for a job to complete Avg. Waiting time (w avg ) ((t 1 -e 1 ) + (t 2 -e 2 )+ … + (t n -e n ))/n or (w 1 +w 2 + … +w n )/n SecondsSystem-centric metric quantifying the average waiting time that an I/O request experiences Response time/ turnaround time titi SecondsUser-centric metric quantifying the turnaround time for a specific I/O request i NameNotationUnitsDescription Variance in Response time E[(t i – t avg ) 2 ]Seconds 2 User-centric metric that quantifies the statistical variance of the actual response time (t i ) experienced by an I/O request i from the expected value (t avg ) Variance in Wait time E[(w i – w avg ) 2 ]Seconds 2 User-centric metric that quantifies the statistical variance of the actual wait time (w i ) experienced by an I/O request i from the expected value (w avg ) Starvation--User-centric qualitative metric that signifies denial of service to a particular I/O request or a set of I/O request due to some intrinsic property of the I/O scheduler

Assumptions for Disk Scheduling Algorithms Disk has 200 tracks numbered 0 to 199 – (with 0 being outermost and 199 being innermost). Head when in its fully retracted position is on track 0. Head assembly extends to its maximum span from its resting position when it is on track 199.

First-Come First Served t3 t1 t4 t2 head

Shortest Seek Time First t3 t1 t4 t2 head

Scan (elevator algorithm) t3 t1 t4t2 head Outermost track Innermost track t6 t5

C-Scan (Circular Scan) t3 t1 t4t2 head Outermost track Innermost track t6 t5 Retract

Look and C-Look

Disk Scheduling Summary Choice of scheduling algorithm depends on a number of factors including expected layout, storage allocation policy, and electro- mechanical capabilities of disk drive. Typically, some variant of LOOK or C-LOOK is used for disk scheduling. We covered other algorithms more from the point of completeness than as viable choices for implementation in a real system.

Comparison of the Algorithms Requests FCFS Response time SSFT LOOK R1 (cyl 20)37155 R2 (cyl 17) R3 (cyl 55) R4 (cyl 35) R5 (cyl 25)7422 R6 (cyl 78) R7 (cyl 99) Average

10.10 Solid State Drive

10.11 Evolution of I/O Buses and Device Drivers Plug and Play (Solves 3 rd party problem) Parallel Buses (e.g. PCI) Serial Buses – USB (Microsoft/Intel) USB 1.0: 1.5Mb/s USB 2.0: 60Mb/s – Firewire (Apple) 100 Mb/s – Why serial? Smaller Cheaper No cross-talk Serial signaling can be operated faster than parallel (Higher frequencies) Graphics Connections (connecting 3-D graphics controller card to motherboard) – Advanced Graphics Port (AGP) – PCI Express (PCI-e)

Dynamic Loading of Device Drivers Device drivers can be Plug and Play New device is connected, generates interrupt OS looks through its list of device drivers and finds correct one* Dynamically Loads and links driver into memory *If no driver found has to request user supply driver

Putting it all Together

10.12 Summary Mechanisms for communication between processor and I/O devices including programmed I/O and DMA. Device controllers and device drivers. Buses in general and evolution of I/O buses in particular, found in modern computer systems. Disk storage and disk-scheduling algorithms.