High Speed Data Acquisition Architectures. Some Basic Architectures Non-Buffered (streaming) FIFO Buffered Multiplexed RAM Ping Pong Multiplexed RAM Dual.

Slides:



Advertisements
Similar presentations
1 UNIT I (Contd..) High-Speed LANs. 2 Introduction Fast Ethernet and Gigabit Ethernet Fast Ethernet and Gigabit Ethernet Fibre Channel Fibre Channel High-speed.
Advertisements

Evaluation of On-Chip Interconnect Architectures for Multi-Core DSP Students : Haim Assor, Horesh Ben Shitrit 2. Shared Bus 3. Fabric 4. Network on Chip.
Accessing I/O Devices Processor Memory BUS I/O Device 1 I/O Device 2.
Interfacing mixed signal peripherals by protocols of packet type Emil Gueorguiev Saramov Angel Nikolaev Popov Computer Systems Department, Technical University.
The ESA MUSIC Project Design of DSP HW and Analog TX/RX ends Advanced Mobile Satellite Systems & Technologies presentation days ESA/ESTEC – November.
Interfacing to the Analog World
Chapter 5 The System Unit.
ATM Switch Architectures
The ARM7TDMI Hardware Architecture
Super Fast Camera System Performed by: Tokman Niv Levenbroun Guy Supervised by: Leonid Boudniak.
t Popularity of the Internet t Provides universal interconnection between individual groups that use different hardware suited for their needs t Based.
System Unit By Sam Gibbs. System Unit The main part of a personal computer Includes a chassis, microprocessor, main memory, bus, and ports Does not include.
1 COMP 206: Computer Architecture and Implementation Montek Singh Mon., Nov. 18, 2002 Topic: Main Memory (DRAM) Organization – contd.
PH4705/ET4305: A/D: Analogue to Digital Conversion
1 Design of the Front End Readout Board for TORCH Detector 10, June 2010.
BLDC MOTOR SPEED CONTROL USING EMBEDDED PROCESSOR
Using Programmable Logic to Accelerate DSP Functions 1 Using Programmable Logic to Accelerate DSP Functions “An Overview“ Greg Goslin Digital Signal Processing.
GallagherP188/MAPLD20041 Accelerating DSP Algorithms Using FPGAs Sean Gallagher DSP Specialist Xilinx Inc.
Module I Overview of Computer Architecture and Organization.
Multiplexer Multiplexing FDM TDM WDM Front-End Processor Controllers.
Information and Communication Technology Fundamentals Credits Hours: 2+1 Instructor: Ayesha Bint Saleem.
Programmable Solutions in Video Capture/Editing. Overview  Xilinx - Industry Leader in FPGAs/CPLDs High-density, high-speed, programmable, low cost logic.
3 1 3 C H A P T E R Hardware: Input, Processing, and Output Devices.
Types of Computers Mainframe/Server Two Dual-Core Intel ® Xeon ® Processors 5140 Multi user access Large amount of RAM ( 48GB) and Backing Storage Desktop.
Survey of Existing Memory Devices Renee Gayle M. Chua.
1-1 Embedded Network Interface (ENI) API Concepts Shared RAM vs. FIFO modes ENI API’s.
2006 Chapter-1 L3: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill, Inc. 1 Hardware Elements in the Embedded.
Computing and the Web Computer Hardware Components.
Data Handling Stephen Kaye Caltech Data Format in Pipeline 16 Bit data from ADC FPGA combines multiple conversions (subtract 5 reset, add.
DIGITAL CONTROL INTERFACES MH0307 PLC & DATA ACQUISITION SYSTEMS DEPARTMENT OF MECHATRONICS ENGINEERING SRM UNIVERSITY.
Owner: VBHUSales Training 03/15/2013 Cypress Confidential IDT 72T36135M vs. Cypress CYF072x Video Buffering Applications High density FIFOs with unmatched.
PART 6: (1/2) Enhancing CPU Performance CHAPTER 16: MICROPROGRAMMED CONTROL 1.
Alexei SemenovGeneric Digitizer Generic Digitizer 10MHZ 16 bit 6U VME Board.
Agenda  Mother Board – P4M266  Types Of Mother Boards  Components - Processor - RAM - Cards - Ports and Slots - BIOS.
Embedded Network Interface (ENI). What is ENI? Embedded Network Interface Originally called DPO (Digital Product Option) card Printer without network.
 Historical view:  1940’s-Vacuum tubes  1947-Transistors invented by willliam shockely & team  1959-Integrated chips invented by Texas Instrument.
AT91 Products Overview. 2 The Atmel AT91 Series of microcontrollers are based upon the powerful ARM7TDMI processor. Atmel has taken these cores, added.
© GCSE Computing Computing Hardware Starter. Creating a spreadsheet to demonstrate the size of memory. 1 byte = 1 character or about 1 pixel of information.
DSP Architectures Additional Slides Professor S. Srinivasan Electrical Engineering Department I.I.T.-Madras, Chennai –
Academic PowerPoint Computer System – Architecture.
Macquarie Fields College of TAFE Version 2 – 13 March HARDWARE 4.
THE MICROPROCESSOR A microprocessor is a single chip of silicon that performs all of the essential functions of a computer central processor unit (CPU)
Fundamentals of Programming Languages-II
Chapter 2.
DDRIII BASED GENERAL PURPOSE FIFO ON VIRTEX-6 FPGA ML605 BOARD PART B PRESENTATION STUDENTS: OLEG KORENEV EUGENE REZNIK SUPERVISOR: ROLF HILGENDORF 1 Semester:
1 Level 1 Pre Processor and Interface L1PPI Guido Haefeli L1 Review 14. June 2002.
HIGH SPEED DATA ACQUISITION SYSTEM RENISH THOMAS EECS /08/2015.
Computer Hardware & Processing Inside the Box CSC September 16, 2010.
Lecture Overview Shift Register Buffering Direct Memory Access.
1 Device Controller I/O units typically consist of A mechanical component: the device itself An electronic component: the device controller or adapter.
IBM Cell Processor Ryan Carlson, Yannick Lanner-Cusin, & Cyrus Stoller CS87: Parallel and Distributed Computing.
Physical Memory and Physical Addressing ( Chapter 10 ) by Polina Zapreyeva.
Firmware development for the AM Board
DIRECT MEMORY ACCESS and Computer Buses
CS 704 Advanced Computer Architecture
Popular Microcontrollers and their Selection by Lachit Dutta
Difference Between SOC (System on Chip) and Single Board Computer
Principles of Information Technology
Embedded Systems Design
Group Manager – PXI™/VXI Software
Introducing Embedded Systems and the Microcontrollers
Cache Memory Presentation I
Unit 2 Computer Systems HND in Computing and Systems Development
Introduction to Digital Signal Processors (DSPs)
Overview of Computer Architecture and Organization
Graphics Hardware: Specialty Memories, Simple Framebuffers
Overview of Computer Architecture and Organization
Introduction SYSC5603 (ELG6163) Digital Signal Processing Microprocessors, Software and Applications Miodrag Bolic.
Introduction SYSC5603 (ELG6163) Digital Signal Processing Microprocessors, Software and Applications Miodrag Bolic.
ADSP 21065L.
Presentation transcript:

High Speed Data Acquisition Architectures

Some Basic Architectures Non-Buffered (streaming) FIFO Buffered Multiplexed RAM Ping Pong Multiplexed RAM Dual Port RAM

Streaming Interface Block Diagram

Advantages / Disadvantages of Streaming Advantages –Simple, low cost –If only a small sample block is required, internal DSP RAM can be used for buffering –Processing takes place in real time Disadvantages –Limited sampling speed

FIFO Buffered Block Diagram

Advantages / Disadvantages of FIFO Buffered Advantages –Simple –Allows initial samples to be processed while subsequent samples are collected –Moderate cost, low to moderate density –Fast: 100MHz clock rates readily available Disadvantages –Sequential access, unneeded samples must be unloaded –Calculations cannot be done in place

Multiplexed RAM Block Diagram

Advantages / Disadvantages of Multiplexed RAM Advantages –Low cost –High density –Random access –Calculations can be done in place Disadvantages –More complex than FIFO, requires multiplexers, counters, etc –RAM only available after all data has been collected. Processing of first samples cannot proceed in parallel with subsequent data collection –RAM access time may require that ADC data be demultiplexed into multiple data streams

Ping Pong Multiplexed RAM Block Diagram

Advantages / Disadvantages of Ping Pong Multiplexed RAM Advantages –High density –Random access –One data buffer is always available to DSP/Host, so next data set is collected while first data set is processed –Calculations can be done in place Disadvantages –Complex, requires dual RAM banks, several multiplexers, counters, etc –RAM access time may require that ADC data be demultiplexed into multiple data streams

Dual Port RAM Block Diagram

Advantages / Disadvantages of Dual Port RAM Advantages –Simple –Random access –First data point is available for processing immediately –Calculations can be done in place Disadvantages –Low density, high cost –RAM access time may require that ADC data be demultiplexed into multiple data streams

Interfaces USB /100 LAN Gigabit LAN Parallel Bus (PXI, CPCI, VME, VXI, etc)

USB 2.0 Advantages –Simple hardware –480 Mbps –Widely available on desktops and laptops Disadvantages –Can require substantial software overhead –Sharing bus with over devices limits bandwidth –Must be in close proximity to computer

10/100 LAN Advantages –Widely available on desktops and laptops –Operates over long distances Disadvantages –Typically requires coprocessor –Can require substantial software overhead –Sharing bus with other devices limits bandwidth

Gigabit LAN Advantages –1000 Mbps –Operates over long distances Disadvantages –Typically requires embedded SBC with operating system support –Can require substantial software overhead –Sharing bus with other devices limits bandwidth

Parallel Bus Advantages –Fastest possible data transfer –DSP may not be required for some applications –Can use off the shelf SBC as controller/host processor –Host processor/OS could support other interfaces (e.g. Gigabit LAN) Disadvantages –Expensive (requires SBC) –Size, power consumption

ADC14100-USB Block Diagram

ADC14100-USB Front Panel

ADC14100-USB Rear Panel

ADC14100-USB Features 14 Bit 100 MSPS ADC Analog Devices ADSP DSP 256K x 18, 100 MHz FIFO memory USB 2.0 Interface RS232 Interface Hardware decimator for lower sample rates at full analog bandwidth 3 software selectable clock sources: –Internal 100 MHz oscillator –Internal 80 MHz oscillator –External clock