Feedback: Principles & Analysis Dr. John Choma, Jr. Professor of Electrical Engineering University of Southern California Department of Electrical Engineering-Electrophysics University Park; Mail Code: 0271 Los Angeles, California 90089-0271 213-740-4692 [OFF] 626-915-7503 [HOME] 626-915-0944 [FAX] johnc@almaak.usc.edu (E-MAIL) EE 448 Feedback Principles & Analysis Fall 2001

High Frequency Dynamics Overview Of Lecture Feedback System Representation System Analysis High Frequency Dynamics Open And Closed Loop Damping Factor Open And Closed Loop Undamped Natural Frequency Frequency Response Phase Margin High Speed Transient Dynamics Step Response Rise Time Settling Time Overshoot 65

Gain: Input And Output Variables Open Loop Model Parameters  Zero Frequency Gain  Frequency Of Zero  Frequency Of Dominant Pole  Frequency Of Non–Dominant Pole Frequency Of Zero Can Be Positive (RHP Zero) Or Negative (LHP Zero) Note That A Simple Dominant Pole Model Is Not Exploited Input And Output Variables Input Voltage Or Current Is X(s) Output Voltage Or Current Is Y(s) 66 3

Open Loop Transfer Function 1 – s z o 1 + p 1 2 = A ol (0) 1 – s z o 1 + 2   nol s + A ol (s) = A ol (0) p 2 1 + Damping Factor: Measure Of Relative Stability Measure Of Step Response Overshoot And Settling Time Undamped Natural Frequency: Measure Of Steady State Bandwidth Measure Of "Ringing" Frequency And Settling Time Poles Dominant Pole Implies Complex Poles Imply Identical Poles Imply = 1 2  ol  nol = p 1 2  ol >> 1  ol < 1  ol = 1 67 4

Closed Loop Transfer Function Loop Gain (Return Ratio w/r To Feedback Factor, f ): Closed Loop Gain: (s) = f A ol (0) 1 – s z o 1 + p 1 2 = T (0) 1 – s z o 1 + 2  ol  nol s + T (s) = f A ol (s) = A cl (0) 1 – s z o 1 + 2   ncl s + Obtained Through Substitution Of Open Loop Gain Relationship Into Closed Loop Gain Expression A cl 68

Closed Loop Parameters 1 – s z o 1 + p 1 2 = A ol (0) 1 – s z o 1 + 2   nol s + A ol (s) = A ol (0) (s) = A cl (0) 1 – s z o 1 + 2   ncl s + A cl Closed Loop Damping Factor: Closed Loop Undamped Frequency: "DC" Closed Loop Gain: T(0) Large For Intentional Feedback T(0) Possibly Large For Parasitic Feedback =  ol 1 + T (0) – T (0) 1 +  nol 2 z o  cl T (0)  f A ol (0)  ncl = nol 1 + T (0) A cl (0)  1 f 69

Closed Loop General Comments =  ol 1 + T (0) – T (0) 1 +  nol 2 z o  cl  ncl =  nol 1 + T (0) Damping Factor Potential Instability Increases With Diminishing Damping Factor Potential Instability Strongly Aggravated By Large Loop Gain Note: Open Loop Damping Attenuation By Factor Of Square Root Of One Plus "DC" Loop Gain For Intentional Feedback Having Closed Loop Gain Of (1/f ), Worst Case Is Unity Gain (f = 1), Corresponding To Maximal T(0) Open Loop Zero Closed Loop Damping Diminished, Thus Potential Instability Aggravated, For Right Half Plane Open Loop Zero Closed Loop Damping Increased, Thus Potential Instability Diminished, For Left Half Plane Open Loop Zero Undamped Frequency Measure Of Closed Loop Bandwidth Closed Loop Bandwidth Increases By Square Root Of One Plus "DC" Loop Gain, In Contrast To Increase By One Plus "DC" Loop Gain Predicted By Dominant Pole Analysis 70

Step Response Example Of Damping Factor Effect Transmission Zero Assumed To Lie At Infinitely Large Frequency  t n 71

Unity Loop Gain Frequency Substitutions: Phase Margin ) =  z o p 1 – tan –1 2  ( v Unity Loop Gain Frequency Assumes Frequencies Of Zero And Second Pole Are Larger Than Substitutions: Phase Margin Difference Between Actual Loop Gain Phase Angle And –180; A Safety Margin For Closed Loop Stability Approximate Phase Margin: Since Can Be Negative, k Can Be A Negative Number Result Is Meaningful Only For  u  T(0) p 1  u k p o – 1 + p 2 = k  u z o = k  u k  1 + k T(0) T(0) – tan –1 tan –1  m   (k) k o  k p > 1 72

Phase Margin Characteristic Phase Margin (deg.) 120 100 T(0) = 1 80 T(0) = 5 60 40 20 T(0) = 100 k -1 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 -20 -40 -60 73

Circuit Response Parameters cl (0) 1 – s z o 1 + 2   ncl s +  u  T(0) p 1 p 2 = k p  u z o = k o  u A cl k p o – 1 + k  p 2 1 + = 1 2  ol  nol = p 1 2  ncl =  nol 1 + T (0) l Closed Loop Damping Factor: l Closed Loop Undamped Frequency: l Phase Margin: k p = 1 2 k p T (0) 1 + k p T(0) 1 – 1 o + 1 1 – 1 k o  cl  2 k p 1 + T (0) T(0)  ncl =  u   u k p 1 + k T(0) T(0) – tan –1 tan –1  m   (k) 74

Closed Loop Example Calculation Given: Desire Maximally Flat Closed Loop Response, Which Implies Computations: Requisite Phase Margin: In Practical Electronics, Phase Margins In The 60s Of Degrees Are Usually Mandated, Which Requires That The Non-Dominant Pole Frequency Be 2.5 -To- 4 Times Larger Than The Unity Gain Frequency  cl > 1 / 2  cl  k p 2 1 – 1 o   > 3.125 k = k p o – 1 +  k = 1.8 f m  tan –1 1 + k T(0) T(0) –  63.2 8 75

Closed Loop Step Response: Problem Formulation (0) 1 – s z o 1 + 2   ncl s + A cl Problem Setup: (Damped Frequency Of Oscillation) Normalized Variables: (Normalized Time Variable) (Output Normalized To Steady–State Response) (Error Between Steady State And Actual Output Responses)  dcl   ncl 1 –  cl 2 z o  ncl k o p M   x   ncl t y (t) A cl (0) y n (t)  1 – y (t) A cl (0)  (t)  = 1 – s z o 1 + 2  cl  ncl s + Y (s) A cl (0) Y n (s)  76

Closed Loop Step Response: Solution 1 – s z o 1 + 2  cl  ncl s + Y n y n (t) = 1 –  (t) (x) = 1 + 2 M  cl + 1 – 1/2 Solution: Assumptions: (Underdamped Closed Loop Response) (Satisfied For Right Half Plane Zero)  e –  cl x x 1 –  cl 2 +  Sin x   ncl t z o  ncl k o p M   M 1 –  cl 2 1 + = tan –1   cl < 1 z o +  cl  ncl > 0 77

Closed Loop Step Response Example #1 78

Closed Loop Step Response Example #2 79

Closed Loop Settling Time (x) = 1 + 2 M  cl + 1 – 1/2  e –  cl x x 1 –  cl 2 +  Sin y n (x) = 1 –  (x) Observations Magnitude Of Error Term Decreases Monotonically With x Maxima Of Error Determined By Setting Derivative Of Error Term With Respect To x To Zero Maxima Are Periodic With Period  First Maximum Of Error Establishes Undershoot Point Determine Second Maximum And Constrain To Desired Minimal Error Procedure Let Be The Normalized Time Corresponding To Second Error Maximum Let Be The Magnitude Of Error Corresponding To If Is The Desired Settling Error, Represents The Settling Time Of the Circuit  m x m  m x m 80

Closed Loop Settling Time Results (x) = 1 + 2 M  cl + 1 – 1/2  e –  cl x x 1 –  cl 2 +  Sin y n (x) = 1 –  (x)  + tan –1 1 –  cl 2 + M = 1 1 –  cl 2 Results: For Large M (Far Right Half Plane Zero): x m = 1 + 2 M  cl +  m e –  cl x m  1 –  cl 2 2  4 – k p x m   –  k p 4 –  m  exp 81

Closed Loop Settling Time Example Requirements Settling To Within One Percent In 1 nSEC Assume Zero Is In Far Right Half Plane (Reasonable Approximation For Common Gate And Compensated Source Follower; First Order Approximation For Common Source) Assume Very Large "DC" Loop Gain Computations Second Pole Must Be At Least 2.7 Times Larger Than Unity Gain Frequency Required Phase Margin: –  k p 4 –  m  exp  0.01  k p > 2.73 ; 2  4 – k p x m =  ncl t m  = 5.575   ncl  2  (887.2 MHz) ;  ncl   u k p   u  2  (537 MHz) tan –1 f m  ( k p ) = 69.9  82