Asynchronous Logic Automata Analog Logic Automata David Dalrymple April 17, 2008 1

Asynchronous Logic Automata

Supercomputer

Supercomputer Code

Architecture

Cellular Microcode Each cell a bit

Cellular Microcode Each cell a bit

Logic CA AND OR XOR NAND Each processor a bit, each bit a processor.

Architecture is software.

Logic CA is synchronous T=0 T=1 T=2 T=3

Asynchronous Logic Clocking keeps data in sync Sometimes we care exactly when data is ready Clocking everything wastes energy, time Sometimes we don't care Don't need clocks to synchronize Asynchronous is just clever synchronization Look at data dependencies

Asynchronous Logic Traditional architectures have very complex data dependencies Most asynchronous logic design has lived with these “Globally asynchronous, locally synchronous”

Data dependencies local

Allow Inaction (0,1,X)

Charge conservation

Consequences of ALA Power savings from Active elements everywhere Clocking Charge conservation Flexible interconnect Fan-out, fan-in free No impedance issues Active elements everywhere Propagate at gate delay cm/10ns

ALA Simulator

(Work of Kailiang Chen) Analog Logic Automata (Work of Kailiang Chen) 20

Soft Computation using Analog Logic Analog domain random variable Px (X=0) & Px (X=1) Digital domain each binary variable { 0 / 1 }

Example 2 -- Xor

3x3 Array Layout 25