1January 18, 2006irk Rich Katz, Grunt Engineer NASA Office of Logic Design Some SEE Testing Considerations for the RTAX-S Series Devices

2January 18, 2006irk V PUMP Can use internal charge pump or external bias –Internal: Ground V PUMP pin –External: 3.0V V PUMP 3.6V V PUMP Supply Voltage (External Pump) In low-power mode, V PUMP will be used to access an external charge pump (if the user desires to bypass the internal charge pump to further reduce power). The device starts using the external charge pump when the voltage level on V PUMP reaches 3V. In normal device operation, when using the internal charge pump, V PUMP should be tied to GND. When V PUMP = 3V, it shuts off the internal charge pump.

3January 18, 2006irk Devices Test All Devices –RTAX250S(4 small tiles) –RTAX1000S(9 regular tiles) –RTAX2000S(16 regular tiles) –RTAX4000S(when available) The devices layout is not the same. –In particular, consider the clock distribution system. –The RTAX250S consists of 4 small tiles, different than the other models.

4January 18, 2006irk Clock Testing Test All Devices (previous slide) Many Types of Clocks –HCLK (4 per chip) Single Ended Differential (LVDS or PECL) Voltage Referenced –Routed Array Clock (4 per chip) Single Ended Differential (LVDS or PECL) Voltage Referenced Use all parts of the chip –Software will disable clock distribution branches that are not used. Real-time monitoring required for clock upset detection.

5January 18, 2006irk Carry Chain RTAX-S Introduced Carry Chain –Hardwired logic Very high speed –Any input to carry chain output (FCO): 0.7 ns max for a -1 speed grade Must measure propagation of transients through this structure. RTAX-S Two-Bit Carry Logic

6January 18, 2006irk RTAX-S SuperCluster RTAX-S architectural elements to be tested.

7January 18, 2006irk I/O Upsets Non-hardened I/O Cells except for clock The RTAX-S single-ended, differential, and voltage-referenced I/O structures are not radiation-tolerant and are subject to SEE. Source: RTAX-S Radiation-Tolerant Features and Mitigation Techniques, January 2005, Actel Corporation. Note: Flip-flops in the I/O Cells are SEU hardened.

8January 18, 2006irk I/O Upsets, 3.3V CMOS Non-hardened I/Os except for clock RTAX-S Device Two stages of a I/O weave using unbonded I/Os. N pulses will be propagated through the chain and the counters will instrument for upsets on rising and falling edges. On-chip monitors provide sensitive I/O upset detection (although in the radiation environment). Counter

9January 18, 2006irk Differential I/O Connections LVDS and PECL use the same circuit topology. OUTPUT_PECL INPUT_PECL

10January 18, 2006irk I/O Upsets, Differential Non-hardened I/Os except for clock RTAX-S Device Two stages of a differential I/O weave using bonded I/Os. N pulses will be propagated through the chain and the counters will instrument for upsets on rising and falling edges. On-chip monitors provide sensitive I/O upset detection (although in the radiation environment). Counter Board-level resistors, 4 per differential pair, not shown. Specific resistor values will support either PECL or LVDS I/Os with an identical topology.

11January 18, 2006irk I/O Upsets, Flip-Flops RTAX-S I/O Cluster I/O Modules contain input, output, and enable flip-flops. Unbonded I/Os will be used to test the InReg and OutReg flip-flops. EnReg will not initially be tested. These flip-flops are designed with TMR and its expected that they are SEU hard. Like the supercluster, the I/O Cluster also contains TX, RX, and B modules.

12January 18, 2006irk Clock Management AX instrumentation chip provides both single ended and differential clocks to the RTAX-S DUT ns total delay 250 ps steps CLK2 CLK1 20 MHz Programmable Divider Mux Multiply (1 to 64) DIVj Mux DUT AX PLL 150 MHz 6.7 ns FREQUNCIES LOW HIGH / x1 / x2 etc. 60 x3 80 x4 100 x5 120 x6 140 x7 160 x8