Nano-Electromechanical Random Access Memory (NEMRAM) Hei Kam Department of EECS, UC Berkeley May 9, 2005 EE241Advanced Digital ICs Final Project
Why New Memory Structure? Fast DRAM, Dense SRAM Dense,Cheap Media Storage Density Speed SRAM DRAM Flash Disk V. Subramanian EE231 Lecture Notes Gaps in the memory space MRAM/FeRAM/PCRAM/ ORAM? Lacking features: Low cost CMOS compatible Scalable Reliable
How about NEMRAM? Structure and Operation Air Top Electrode Bottom Electrode Mechanical Nanowire Actuator (Carbon Nanotube/ Silicon Nanowire?) SiO2 V>Vwrite V=0 “0” State “1” State V>Vwrite V=0 Circuit Element & Model Surface adhesion (“Stiction”) – non-volatile,no static power Large Roff/Ron ratio - Reliable (MRAM: Roff/Ron <2)
2T-1NEM SRAM: Fast DRAM, Dense SRAM WL BL WL=1 WL=0 BL precharged to Vread Read Operation BL=1 WL=1 WL=0 BL=0 Write“1” Write “0” Write Operation Drop-in replacement for 6T-SRAM: Similar R/W schemes NMOS-only: Saves Area Differential Signal Available: Noise immunity
Cross Point (XP) NEMRAM: Media Storage BL TWL BWL Write Operation Selected row Vwrite GND “0” “1” BL TWL BWL Read Operation Vread GND Selected row I = 0 I = Iread No Transistor is needed –Vertically stackable (3D), Ultra high density, Low Cost Potential platform for Defect Tolerance Architecture
Scalability & Performance of NEMRAM Area, Vwrite tread and twrite Assume constant dim. scaling Adjust Ws for desirable result Low pressure operation L=0.5um tgap=50nm tsi=25nm W=0.25um (min. feature size) Matlab Simulation results F/2 F 2F Layout Area=6F2
NEMRAM vs MRAM NEMRAM MRAM Area 6F2 4F2 Roff/Ron Large <2 tread ~10ps ~10ns twrite Differential Yes No New Material No(?) Endurance >1012 1015 IEDM 2004 23.1.1
Summary NEMRAM shows its promise as a low cost, high density and nonvolatile memory with reasonable R/W performance fills the gap in the memory space Plus: -Long Endurance (>1012 cycles, RF MEMS Switches) -Soft Error Immunity -Unlike MRAM/FeRAM , no new material is needed -CMOS/MEMS Compatible