CS150 Midterm2 Review Joy! Another midterm

Overview of things to review Flip-flop, Latch Edge triggered, level sensitive, completely transparent Timing analysis. Sync/Async Set Reset Enable FSM Word description -> implementation Mealy, Moore State minimization State Encoding Optimization Datapath, Control CS 150 - Fall 2000 - Introduction - 2

CS 150 - Fall 2000 - Introduction - 3 Sequential Circuits Circuits with history This is a General Concept Things to looks over for midterm: Circuit Elements used in Sequential Circuits to keep track of the “history” Flip flops, Latches Edge triggered, level sensitive, completely transparent Timing analysis FSM Understanding word problems Identifying input, output to combinational part of FSM State assignment (optimization) Generating actual circuit implementation CS 150 - Fall 2000 - Introduction - 3

CS 150 - Fall 2000 - Introduction - 4 Sequential Circuits Circuits with Feedback Outputs = f(inputs, past inputs, past outputs) Basis for building "memory" into logic circuits Door combination lock is an example of a sequential circuit State is memory State is an "output" and an "input" to combinational logic Combination storage elements are also memory new equal reset value C1 C2 C3 mux control multiplexer comb. logic comparator state clock equal open/closed CS 150 - Fall 2000 - Introduction - 4

CS 150 - Fall 2000 - Introduction - 5 RS Latch Not really used much in real designs Mainly used because it is simple and easy to understand. MAKE SURE that you know how timing works for this thing MAKE SURE that you know how timing works for All the other Flip flop and Latches also. You probably want to remember a little about the implementation also, its helps you to remember how to analyze things. CS 150 - Fall 2000 - Introduction - 5

Memory with Cross-coupled Gates Cross-coupled NOR gates Similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1) Cross-coupled NAND gates Similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0) R S Q Q' R S Q Q Q' S' R' R' S' Q CS 150 - Fall 2000 - Introduction - 6

CS 150 - Fall 2000 - Introduction - 7 Timing Behavior R S Q Q' Reset Hold Set Reset Set Race 100 R S Q \Q CS 150 - Fall 2000 - Introduction - 7

State Behavior of R-S latch Truth table of R-S latch behavior Q Q' 0 1 Q Q' 1 0 Q Q' 0 0 Q Q' 1 1 S R Q 0 0 hold 0 1 0 1 0 1 1 1 unstable This doesn’t have anything to do with FSM state diagram so if it confuses you then just ignore it. You do however need to know how a RS latch functions CS 150 - Fall 2000 - Introduction - 8

Theoretical R-S Latch Behavior SR=11 Anybody else think this thing looks like a monkey head? SR=10 SR=00 SR=01 SR=00 SR=10 Q Q' 0 1 Q Q' 1 0 Q Q' 0 0 Q Q' 1 1 SR=01 SR=10 SR=01 SR=01 SR=10 SR=11 SR=11 State Diagram States: possible values Transitions: changes based on inputs possible oscillation between states 00 and 11 SR=00 SR=00 SR=11 CS 150 - Fall 2000 - Introduction - 9

Observed R-S Latch Behavior Very difficult to observe R-S latch in the 1-1 state One of R or S usually changes first Ambiguously returns to state 0-1 or 1-0 A so-called "race condition" Or non-deterministic transition Q Q' 0 1 Q Q' 1 0 Q Q' 0 0 SR=10 SR=01 SR=00 SR=11 SR=00 CS 150 - Fall 2000 - Introduction - 10

R-S Latch Analysis Break feedback path Q(t) R Q Q(t+) S Q' R S S R Q(t) Q(t+) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 X 1 1 1 X hold reset set not allowed 0 0 1 0 X 1 Q(t) R S characteristic equation Q(t+) = S + R’ Q(t) CS 150 - Fall 2000 - Introduction - 11

CS 150 - Fall 2000 - Introduction - 12 Gated R-S Latch Control when R and S inputs matter Otherwise, the slightest glitch on R or S while enable is low could cause change in value stored enable' S' Q' Q R' R S Set Reset S' R' enable' Q Q' 100 This creates a LEVEL SENSITIVE RS latch. CS 150 - Fall 2000 - Introduction - 12

CS 150 - Fall 2000 - Introduction - 13 Clocks Used to keep time Wait long enough for inputs (R' and S') to settle Then allow to have effect on value stored Clocks are regular periodic signals Period (time between ticks) Duty-cycle (time clock is high between ticks - expressed as % of period) duty cycle (in this case, 50%) period CS 150 - Fall 2000 - Introduction - 13

CS 150 - Fall 2000 - Introduction - 14 Clocks (cont’d) Controlling an R-S latch with a clock Can't let R and S change while clock is active (allowing R and S to pass) Only have half of clock period for signal changes to propagate Signals must be stable for the other half of clock period clock' S' Q' Q R' R S clock R' and S' changing stable CS 150 - Fall 2000 - Introduction - 14

CS 150 - Fall 2000 - Introduction - 15 Cascading Latches Connect output of one latch to input of another How to stop changes from racing through chain? Need to control flow of data from one latch to the next Advance from one latch per clock period Worry about logic between latches (arrows) that is too fast clock R S Q Q' CS 150 - Fall 2000 - Introduction - 15

Master-Slave RS (flip flop??) Another Thing you need to stuff in your brain for this test Again make sure you know the timing for this sucker Also don’t for get the 1’s catching problem, professor Katz seems to like this one. CS 150 - Fall 2000 - Introduction - 16

Master-Slave Structure Break flow by alternating clocks (like an air-lock) Use positive clock to latch inputs into one R-S latch Use negative clock to change outputs with another R-S latch View pair as one basic unit master-slave flip-flop twice as much logic output changes a few gate delays after the falling edge of clock but does not affect any cascaded flip-flops master stage slave stage P P' CLK R S Q Q' CS 150 - Fall 2000 - Introduction - 17

CS 150 - Fall 2000 - Introduction - 18 The 1s Catching Problem In first R-S stage of master-slave FF 0-1-0 glitch on R or S while clock is high "caught" by master stage Leads to constraints on logic to be hazard-free master stage slave stage P P' CLK R S Q Q' Set 1s catch S R CLK P P' Q Q' Reset Master Outputs Slave Outputs CS 150 - Fall 2000 - Introduction - 18

D Flip-Flops (Ah something that people actually use for a change) This is the bread and butter of Logic Design so MAKE SURE you know EDGE TRIGGERED flip flops like the back of your hand. (fortunately they are very easy to understand functionally which is why people like to use them) CS 150 - Fall 2000 - Introduction - 19

CS 150 - Fall 2000 - Introduction - 20 D Flip-Flop Make S and R complements of each other Eliminates 1s catching problem Can't just hold previous value (must have new value ready every clock period) Value of D just before clock goes low is what is stored in flip-flop Can make R-S flip-flop by adding logic to make D = S + R' Q This is also an Edge triggered Flip-flop even though it doesn’t say on this slide D Q Q' master stage slave stage P P' CLK R S 10 gates CS 150 - Fall 2000 - Introduction - 20

Edge-Triggered Flip-Flops More efficient solution: only 6 gates sensitive to inputs only near edge of clock signal (not while high) Q D Clk=1 R S D’ Q’ holds D' when clock goes low negative edge-triggered D flip-flop (D-FF) 4-5 gate delays must respect setup and hold time constraints to successfully capture input holds D when clock goes low characteristic equation Q(t+1) = D CS 150 - Fall 2000 - Introduction - 21

Edge-Triggered Flip-Flops (cont’d) Step-by-step analysis Q D Clk=0 R S D’ Q new D Clk=0 R S D D’ new D  old D when clock goes high-to-low data is latched when clock is low data is held CS 150 - Fall 2000 - Introduction - 22

Edge-Triggered Flip-Flops (cont’d) Positive edge-triggered Inputs sampled on rising edge; outputs change after rising edge Negative edge-triggered flip-flops Inputs sampled on falling edge; outputs change after falling edge 100 D CLK Qpos Qpos' Qneg Qneg' positive edge-triggered FF negative edge-triggered FF CS 150 - Fall 2000 - Introduction - 23

CS 150 - Fall 2000 - Introduction - 24 Timing Make sure you know how to analyze on a Clock cycle by clock cycle bases first Setup and hold times are really just a general concept that you don’t need to know in deep detail. Pretty important although probably much more important in EE141 CS 150 - Fall 2000 - Introduction - 24

CS 150 - Fall 2000 - Introduction - 25 Timing Methodologies Rules for interconnecting components and clocks Guarantee proper operation of system when strictly followed Approach depends on building blocks used for memory elements Focus on systems with edge-triggered flip-flops Found in programmable logic devices Many custom integrated circuits focus on level-sensitive latches Basic rules for correct timing: (1) Correct inputs, with respect to time, are provided to the flip-flops (2) No flip-flop changes state more than once per clocking event CS 150 - Fall 2000 - Introduction - 25

Timing Methodologies (cont’d) Definition of terms clock: periodic event, causes state of memory element to change; can be rising or falling edge, or high or low level setup time: minimum time before the clocking event by which the input must be stable (Tsu) hold time: minimum time after the clocking event until which the input must remain stable (Th) input clock Tsu Th data D Q D Q clock there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized stable changing data clock CS 150 - Fall 2000 - Introduction - 26

Comparison of Latches and Flip-Flops D Q D CLK Qedge Qlatch CLK positive edge-triggered flip-flop D Q G CLK transparent (level-sensitive) latch behavior is the same unless input changes while the clock is high CS 150 - Fall 2000 - Introduction - 27

CS 150 - Fall 2000 - Introduction - 28 Next slide important! Although to me a “Master Slave” D flip-flop is no different functionally than the “Edge Triggered” flip-flop On the other hand a “Master Slave RS” does have a 1s catching problem CS 150 - Fall 2000 - Introduction - 28

Comparison of Latches and Flip-Flops (cont’d) Type When inputs are sampled When output is valid unclocked always propagation delay from input change latch level-sensitive clock high propagation delay from input change latch (Tsu/Th around falling or clock edge (whichever is later) edge of clock) master-slave clock high propagation delay from falling edge flip-flop (Tsu/Th around falling of clock edge of clock) negative clock hi-to-lo transition propagation delay from falling edge edge-triggered (Tsu/Th around falling of clock flip-flop edge of clock) CS 150 - Fall 2000 - Introduction - 29

Typical Timing Specifications Positive edge-triggered D flip-flop Setup and hold times Minimum clock width Propagation delays (low to high, high to low, max and typical) Th 5ns Tw 25ns Tplh 25ns 13ns Tphl 40ns 25ns Tsu 20ns D CLK Q all measurements are made from the clocking event that is, the rising edge of the clock CS 150 - Fall 2000 - Introduction - 30

Cascading Edge-triggered Flip-Flops Shift register New value goes into first stage While previous value of first stage goes into second stage Consider setup/hold/propagation delays (prop must be > hold) CLK IN Q0 Q1 D Q OUT 100 IN Q0 Q1 CLK CS 150 - Fall 2000 - Introduction - 31

Cascading Edge-triggered Flip-Flops (cont’d) Why this works Propagation delays exceed hold times Clock width constraint exceeds setup time This guarantees following stage will latch current value before it changes to new value In Q0 Q1 CLK Tsu 4ns Tsu 4ns timing constraints guarantee proper operation of cascaded components Tp 3ns Tp 3ns assumes infinitely fast distribution of the clock Th 2ns Th 2ns CS 150 - Fall 2000 - Introduction - 32

Summary of Latches and Flip-Flops Development of D-FF Level-sensitive used in custom integrated circuits can be made with 4 switches Edge-triggered used in programmable logic devices Good choice for data storage register Historically J-K FF was popular but now never used Similar to R-S but with 1-1 being used to toggle output (complement state) Good in days of TTL/SSI (more complex input function: D = JQ' + K'Q Not a good choice for PALs/PLAs as it requires 2 inputs Can always be implemented using D-FF Preset and clear inputs are highly desirable on flip-flops Used at start-up or to reset system to a known state CS 150 - Fall 2000 - Introduction - 33

Metastability and Asynchronous inputs Not terribly important Know that it exist Know why it exists Asynchronous input to a synchronized circuit. Triggered by setup/hold time violations Know how to minimize the chance of it happening. Add synchronizing flip flops on asynchronous inputs CS 150 - Fall 2000 - Introduction - 34

Metastability and Asynchronous inputs Clocked synchronous circuits Inputs, state, and outputs sampled or changed in relation to a common reference signal (called the clock) E.g., master/slave, edge-triggered Asynchronous circuits Inputs, state, and outputs sampled or changed independently of a common reference signal (glitches/hazards a major concern) E.g., R-S latch Asynchronous inputs to synchronous circuits Inputs can change at any time, will not meet setup/hold times Dangerous, synchronous inputs are greatly preferred Cannot be avoided (e.g., reset signal, memory wait, user input) CS 150 - Fall 2000 - Introduction - 35

Synchronization Failure Occurs when FF input changes close to clock edge FF may enter a metastable state – neither a logic 0 nor 1 – May stay in this state an indefinite amount of time Is not likely in practice but has some probability logic 1 logic 0 logic 0 logic 1 small, but non-zero probability that the FF output will get stuck in an in-between state oscilloscope traces demonstrating synchronizer failure and eventual decay to steady state CS 150 - Fall 2000 - Introduction - 36

Dealing with Synchronization Failure Probability of failure can never be reduced to 0, but it can be reduced (1) slow down the system clock: this gives the synchronizer more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems (2) use fastest possible logic technology in the synchronizer: this makes for a very sharp "peak" upon which to balance (3) cascade two synchronizers: this effectively synchronizes twice (both would have to fail) asynchronous input Q synchronized input D Q D Clk CS 150 - Fall 2000 - Introduction - 37 synchronous system

Handling Asynchronous Inputs Never allow asynchronous inputs to fan-out to more than one flip-flop Synchronize as soon as possible and then treat as synchronous signal Clocked Synchronizer Synchronous System Async Q0 Async Q0 D Q D Q D Q Input Input Clock Clock D Q Q1 D Q Q1 Clock Clock CS 150 - Fall 2000 - Introduction - 38

Handling Asynchronous Inputs (cont’d) What can go wrong? Input changes too close to clock edge (violating setup time constraint) In Q0 Q1 CLK In is asynchronous and fans out to D0 and D1 one FF catches the signal, one does not inconsistent state may be reached! CS 150 - Fall 2000 - Introduction - 39

CS 150 - Fall 2000 - Introduction - 40 Flip-Flop Features Pretty important stuff Make sure you know Set, Reset Synchronous, Asynchronous, and their differences Enable How timing analysis works when these features are added CS 150 - Fall 2000 - Introduction - 40

CS 150 - Fall 2000 - Introduction - 41 Flip-Flop Features Reset (set state to 0) – R Synchronous: Dnew = R' • Dold (when next clock edge arrives) Asynchronous: doesn't wait for clock, quick but dangerous Preset or set (set state to 1) – S (or sometimes P) Synchronous: Dnew = Dold + S (when next clock edge arrives) Both reset and preset Dnew = R' • Dold + S (set-dominant) Dnew = R' • Dold + R'S (reset-dominant) Selective input capability (input enable/load) – LD or EN Multiplexer at input: Dnew = LD' • Q + LD • Dold Load may/may not override reset/set (usually R/S have priority) Complementary outputs – Q and Q' CS 150 - Fall 2000 - Introduction - 41

CS 150 - Fall 2000 - Introduction - 42 Registers Collections of flip-flops with similar controls and logic Stored values somehow related (e.g., form binary value) Share clock, reset, and set lines Similar logic at each stage Examples Shift registers Counters R S D Q OUT1 OUT2 OUT3 OUT4 CLK IN1 IN2 IN3 IN4 "0" CS 150 - Fall 2000 - Introduction - 42

CS 150 - Fall 2000 - Introduction - 43 Shift Register Holds samples of input Store last 4 input values in sequence 4-bit shift register: D Q IN OUT1 OUT2 OUT3 OUT4 CLK CS 150 - Fall 2000 - Introduction - 43

Universal Shift Register A good Case study Take a good look at it Make sure you know how it works CS 150 - Fall 2000 - Introduction - 44

Universal Shift Register Holds 4 values Serial or parallel inputs Serial or parallel outputs Permits shift left or right Shift in new values from left or right left_in left_out right_out clear right_in output input s0 s1 clock clear sets the register contents and output to 0 s1 and s0 determine the shift function s0 s1 function 0 0 hold state 0 1 shift right 1 0 shift left 1 1 load new input CS 150 - Fall 2000 - Introduction - 45

Design of Universal Shift Register Consider one of the four flip-flops New value at next clock cycle: Nth cell to N-1th cell to N+1th cell Q D CLK clear s0 s1 new value 1 – – 0 0 0 0 output 0 0 1 output value of FF to left (shift right) 0 1 0 output value of FF to right (shift left) 0 1 1 input CLEAR s0 and s1 control mux 1 2 3 Q[N-1] (left) Q[N+1] (right) Input[N] CS 150 - Fall 2000 - Introduction - 46

Shift Register Application You probably don’t need to Memorize these in detail Just look over them make sure they make sense to you CS 150 - Fall 2000 - Introduction - 47

Shift Register Application Parallel-to-serial conversion for serial transmission parallel outputs parallel inputs serial transmission CS 150 - Fall 2000 - Introduction - 48

CS 150 - Fall 2000 - Introduction - 49 Pattern Recognizer Combinational function of input samples In this case, recognizing the pattern 1001 on the single input signal D Q IN OUT1 OUT2 OUT3 OUT4 CLK OUT CS 150 - Fall 2000 - Introduction - 49

CS 150 - Fall 2000 - Introduction - 50 Binary Counter Logic between registers (not just multiplexer) XOR decides when bit should be toggled Always for low-order bit, only when first bit is true for second bit, and so on D Q OUT1 OUT2 OUT3 OUT4 CLK "1" CS 150 - Fall 2000 - Introduction - 50

Four-bit Binary Synchronous Up-Counter Standard component with many applications Positive edge-triggered FFs w/ sync load and clear inputs Parallel load data from D, C, B, A Enable inputs: must be asserted to enable counting RCO: ripple-carry out used for cascading counters high when counter is in its highest state 1111 implemented using an AND gate EN D C B A LOAD CLK CLR RCO QD QC QB QA (2) RCO goes high (3) High order 4-bits are incremented (1) Low order 4-bits = 1111 CS 150 - Fall 2000 - Introduction - 51

CS 150 - Fall 2000 - Introduction - 52 Offset Counters Starting offset counters – use of synchronous load e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, . . . Ending offset counter – comparator for ending value e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000 Combinations of the above (start and stop value) "0" EN D C B A LOAD CLK CLR RCO QD QC QB QA "1" "0" "1" "1" "0" EN D C B A LOAD CLK CLR RCO QD QC QB QA "1" "0" "0" "0" "0" CS 150 - Fall 2000 - Introduction - 52

Sequential Logic Summary Fundamental building block of circuits with state Latch and flip-flop R-S latch, R-S master/slave, D master/slave, edge-triggered D FF Timing methodologies Use of clocks Cascaded FFs work because prop delays exceed hold times Beware of clock skew Asynchronous inputs and their dangers Synchronizer failure: what it is and how to minimize its impact Basic registers Shift registers Pattern detectors Counters CS 150 - Fall 2000 - Introduction - 53

Sequential Logic Implementation Ah… FSMs… Another one of those things that you’d better make sure you know for the midterm. (that means at least one problem related to it on the test) CS 150 - Fall 2000 - Introduction - 54

Sequential Logic Implementation Sequential Circuits Primitive sequential elements Combinational logic Models for representing sequential circuits Finite-state machines (Moore and Mealy) Representation of memory (states) Changes in state (transitions) Basic sequential circuits Shift registers Counters Design procedure State diagrams State transition table Next state functions CS 150 - Fall 2000 - Introduction - 55

Abstraction of State Elements Divide circuit into combinational logic and state Localize feedback loops and make it easy to break cycles Implementation of storage elements leads to various forms of sequential logic Combinational Logic Storage Elements Outputs State Outputs State Inputs Inputs CS 150 - Fall 2000 - Introduction - 56

Forms of Sequential Logic Asynchronous sequential logic – state changes occur whenever state inputs change (elements may be simple wires or delay elements) Synchronous sequential logic – state changes occur in lock step across all storage elements (using a periodic waveform - the clock) Not important for this class Clock CS 150 - Fall 2000 - Introduction - 57

Finite State Machine Representations States: determined by possible values in sequential storage elements Transitions: change of state Clock: controls when state can change by controlling storage elements Sequential Logic Sequences through a series of states Based on sequence of values on input signals Clock period defines elements of sequence In = 0 In = 1 100 010 110 111 001 CS 150 - Fall 2000 - Introduction - 58

How Do We Turn a State Diagram into Logic? Counter Three flip-flops to hold state Logic to compute next state Clock signal controls when flip-flop memory can change Wait long enough for combinational logic to compute new value Don't wait too long as that is low performance D Q OUT1 OUT2 OUT3 CLK "1" CS 150 - Fall 2000 - Introduction - 59

CS 150 - Fall 2000 - Introduction - 60 FSM Design Procedure Start with counters Simple because output is just state Simple because no choice of next state based on input State diagram to state transition table Tabular form of state diagram Like a truth-table State encoding Decide on representation of states For counters it is simple: just its value Implementation Flip-flop for each state bit Combinational logic based on encoding CS 150 - Fall 2000 - Introduction - 60

FSM Design Procedure: State Diagram to Encoded State Transition Table Tabular form of state diagram Like a truth-table (specify output for all input combinations) Encoding of states: easy for counters – just use value current state next state 0 000 001 1 1 001 010 2 2 010 011 3 3 011 100 4 4 100 101 5 5 101 110 6 6 110 111 7 7 111 000 0 010 100 110 011 001 000 101 111 3-bit up-counter CS 150 - Fall 2000 - Introduction - 61

CS 150 - Fall 2000 - Introduction - 62 Implementation Really important MAKE SURE you know how to implement FSM, all the way from word descriptions to circuit implementation. However don’t go and memorize all the different implementations. (there are too many slides) Instead concentrate on how to do it yourself. CS 150 - Fall 2000 - Introduction - 62

CS 150 - Fall 2000 - Introduction - 63 Implementation D flip-flop for each state bit Combinational logic based on encoding notation to show function represent input to D-FF C3 C2 C1 N3 N2 N1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 N1 := C1' N2 := C1C2' + C1'C2 := C1 xor C2 N3 := C1C2C3' + C1'C3 + C2'C3 := C1C2C3' + (C1' + C2')C3 := (C1C2) xor C3 0 0 0 1 1 1 C1 C2 C3 N3 0 1 1 0 C1 C2 C3 N2 1 1 0 0 C1 C2 C3 N1 CS 150 - Fall 2000 - Introduction - 63

Implementation (cont'd) Programmable Logic Building Block for Sequential Logic Macro-cell: FF + logic D-FF Two-level logic capability like PAL (e.g., 8 product terms) D Q Q CS 150 - Fall 2000 - Introduction - 64

CS 150 - Fall 2000 - Introduction - 65 Another Example Shift Register Input determines next state In C1 C2 C3 N1 N2 N3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 1 1 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 100 110 111 011 101 010 000 001 1 N1 := In N2 := C1 N3 := C2 D Q IN OUT1 OUT2 OUT3 CLK CS 150 - Fall 2000 - Introduction - 65

More Complex Counter Example Repeats five states in sequence Not a binary number representation Step 1: Derive the state transition diagram Count sequence: 000, 010, 011, 101, 110 Step 2: Derive the state transition table from the state transition diagram 010 000 110 101 011 Present State Next State C B A C+ B+ A+ 0 0 0 0 1 0 0 0 1 – – – 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 – – – 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 – – – note the don't care conditions that arise from the unused state codes CS 150 - Fall 2000 - Introduction - 66

More Complex Counter Example (cont’d) Step 3: K-maps for Next State Functions 0 0 X 1 0 X A B C C+ 1 1 X 0 0 X X 1 A B C B+ 0 1 X 1 0 X X 0 A B C A+ C+ := A B+ := B' + A'C' A+ := BC' CS 150 - Fall 2000 - Introduction - 67

Self-Starting Counters (cont’d) Re-deriving state transition table from don't care assignment 0 0 1 1 A B C C+ 1 1 1 0 0 1 A B C B+ 0 1 0 0 A B C A+ 010 000 110 101 011 001 111 100 Present State Next State C B A C+ B+ A+ 0 0 0 0 1 0 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 CS 150 - Fall 2000 - Introduction - 68

Self-Starting Counters Start-up States At power-up, counter may be in an unused or invalid state Designer must guarantee it (eventually) enters a valid state Self-starting Solution Design counter so that invalid states eventually transition to a valid state May limit exploitation of don't cares 010 000 110 101 011 001 111 100 implementation on previous slide 010 000 110 101 011 001 111 100 CS 150 - Fall 2000 - Introduction - 69

CS 150 - Fall 2000 - Introduction - 70 State Machine Model Values stored in registers represent the state of the circuit Combinational logic computes: Next state Function of current state and inputs Outputs Function of current state and inputs (Mealy machine) Function of current state only (Moore machine) Inputs Outputs Next State Current State output logic next state logic CS 150 - Fall 2000 - Introduction - 70

State Machine Model (cont’d) Inputs Outputs Next State Current State output logic next state logic States: S1, S2, ..., Sk Inputs: I1, I2, ..., Im Outputs: O1, O2, ..., On Transition function: Fs(Si, Ij) Output function: Fo(Si) or Fo(Si, Ij) Clock Next State State 1 2 3 4 5 CS 150 - Fall 2000 - Introduction - 71

Example: Ant Brain (Ward, MIT) Sensors: L and R antennae, 1 if in touching wall Actuators: F - forward step, TL/TR - turn left/right slightly Goal: find way out of maze Strategy: keep the wall on the right CS 150 - Fall 2000 - Introduction - 72

CS 150 - Fall 2000 - Introduction - 73 Ant Behavior A: Following wall, touching Go forward, turning left slightly B: Following wall, not touching Go forward, turning right slightly D: Hit wall again Back to state A C: Break in wall Go forward, turning right slightly E: Wall in front Turn left until... F: ...we are here, same as state B G: Turn left until... LOST: Forward until we touch something CS 150 - Fall 2000 - Introduction - 73

CS 150 - Fall 2000 - Introduction - 74 Designing an Ant Brain State Diagram L + R L’ R LOST (F) L’ R’ E/G (TL) L + R R A (TL, F) L L’ R’ B (TR, F) L’ R’ R C (TR, F) R’ R’ CS 150 - Fall 2000 - Introduction - 74

Synthesizing the Ant Brain Circuit Encode States Using a Set of State Variables Arbitrary choice - may affect cost, speed Use Transition Truth Table Define next state function for each state variable Define output function for each output Implement next state and output functions using combinational logic 2-level logic (ROM/PLA/PAL) Multi-level logic Next state and output functions can be optimized together CS 150 - Fall 2000 - Introduction - 75

Transition Truth Table Using symbolic states and outputs LOST (F) E/G (TL) A (TL, F) B (TR, F) C (TR, F) R’ L’ R’ R L L’ R L + R state L R next state outputs LOST 0 0 LOST F LOST – 1 E/G F LOST 1 – E/G F A 0 0 B TL, F A 0 1 A TL, F A 1 – E/G TL, F B – 0 C TR, F B – 1 A TR, F ... ... ... ... ... CS 150 - Fall 2000 - Introduction - 76

CS 150 - Fall 2000 - Introduction - 77 Synthesis 5 states : at least 3 state variables required (X, Y, Z) State assignment (in this case, arbitrarily chosen) LOST - 000 E/G - 001 A - 010 B - 011 C - 100 state L R next state outputs X,Y,Z X', Y', Z' F TR TL 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 ... ... ... ... ... 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 it now remains to synthesize these 6 functions CS 150 - Fall 2000 - Introduction - 77

Synthesis of Next State and Output Functions state inputs next state outputs X,Y,Z L R X+,Y+,Z+ F TR TL 0 0 0 0 0 0 0 0 1 0 0 0 0 0 - 1 0 0 1 1 0 0 0 0 0 1 - 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 1 - 1 0 1 0 0 0 1 0 0 1 1 - 0 1 0 0 0 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 - 0 0 1 1 0 1 0 1 1 - 0 1 0 0 1 1 0 0 1 1 - 1 0 1 0 1 1 0 1 0 0 - 0 1 0 0 1 1 0 1 0 0 - 1 0 1 0 1 1 0 e.g. TR = X + Y Z X+ = X R’ + Y Z R’ = R’ TR CS 150 - Fall 2000 - Introduction - 78

Circuit Implementation Outputs are a function of the current state only - Moore machine L R F TR TL Next State Current State output logic next state logic X+ Y+ Z+ X Y Z CS 150 - Fall 2000 - Introduction - 79

Don’t Cares in FSM Synthesis What happens to the "unused" states (101, 110, 111)? Exploited as don't cares to minimize the logic If states can't happen, then don't care what the functions do if states do happen, we may be in trouble 000 (F) 001 (TL) 010 (TL, F) 011 (TR, F) 100 (TR, F) R’ L’ R’ R L L’ R L + R 111 101 110 Ant is in deep trouble if it gets in this state CS 150 - Fall 2000 - Introduction - 80

CS 150 - Fall 2000 - Introduction - 81 State Minimization Fewer states may mean fewer state variables High-level synthesis may generate many redundant states Two state are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same Two conditions for two states to be equivalent: 1) Output must be the same in both states 2) Must transition to equivalent states for all input combinations CS 150 - Fall 2000 - Introduction - 81

CS 150 - Fall 2000 - Introduction - 82 Ant Brain Revisited Any equivalent states? LOST (F) E/G (TL) A (TL, F) B (TR, F) C (TR, F) R’ L’ R’ R L L’ R L + R CS 150 - Fall 2000 - Introduction - 82

CS 150 - Fall 2000 - Introduction - 83 New Improved Brain Merge equivalent B and C states Behavior is exactly the same as the 5-state brain We now need only 2 state variables rather than 3 LOST (F) E/G (TL) A (TL, F) B/C (TR, F) R’ L’ R’ R L L’ R L + R CS 150 - Fall 2000 - Introduction - 83

New Brain Implementation state inputs next state outputs X,Y L R X',Y' F TR TL 0 0 0 0 0 0 1 0 0 0 0 - 1 0 1 1 0 0 0 0 1 - 0 1 1 0 0 0 1 0 0 1 1 0 0 1 0 1 - 1 0 1 0 0 1 0 1 1 - 0 1 0 0 1 1 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 1 0 1 - 0 1 1 0 1 1 1 - 0 1 1 1 1 0 1 1 - 1 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 0 X X+ Y R L 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 1 X Y+ Y R L 1 0 1 1 X F Y R L 0 0 1 0 X TR Y R L 0 1 0 1 X TL Y R L CS 150 - Fall 2000 - Introduction - 84

Mealy vs. Moore Machines Big concept! Know this one! Mealy Output is a function of input Note, if input is asynchronous then output might be asynchronous also. That makes mealy more dangerous to use Moore Output is not a function of input, instead is purely a function of the state This guarantees that output is synchronous. Makes Moore machines more robust. Also introduces a clock edge difference in between change of input and output. That means some problems can only be solved by a mealy. CS 150 - Fall 2000 - Introduction - 85

Mealy vs. Moore Machines Moore: outputs depend on current state only Mealy: outputs depend on current state and inputs Ant brain is a Moore Machine Output does not react immediately to input change We could have specified a Mealy FSM Outputs have immediate reaction to inputs As inputs change, so does next state, doesn’t commit until clocking event A L’ R’ / TR, F L / TL L’ R / TL, F react right away to leaving the wall CS 150 - Fall 2000 - Introduction - 86

Arg… So many slides of examples! Again don’t kill yourself trying to memorize every detail of these examples Just make sure they make sense to you CS 150 - Fall 2000 - Introduction - 87

Specifying Outputs for a Moore Machine Output is only function of state Specify in state bubble in state diagram Example: sequence detector for 01 or 10 current next reset input state state output 1 – – A 0 0 A B 0 0 1 A C 0 0 0 B B 0 0 1 B D 0 0 0 C E 0 0 1 C C 0 0 0 D E 1 0 1 D C 1 0 0 E B 1 0 1 E D 1 D/1 E/1 B/0 A/0 C/0 1 reset CS 150 - Fall 2000 - Introduction - 88

Specifying Outputs for a Mealy Machine Output is function of state and inputs Specify output on transition arc between states Example: sequence detector for 01 or 10 current next reset input state state output 1 – – A 0 0 0 A B 0 0 1 A C 0 0 0 B B 0 0 1 B C 1 0 0 C B 1 0 1 C C 0 B A C 0/1 0/0 1/1 1/0 reset/0 CS 150 - Fall 2000 - Introduction - 89

Comparison of Mealy and Moore Machines Mealy Machines tend to have less states Different outputs on arcs (n^2) rather than states (n) Moore Machines are safer to use Outputs change at clock edge (always one cycle later) In Mealy machines, input change can cause output change as soon as logic is done – a big problem when two machines are interconnected – asynchronous feedback Mealy Machines react faster to inputs React in same cycle – don't need to wait for clock In Moore machines, more logic may be necessary to decode state into outputs – more gate delays after state feedback inputs outputs reg combinational logic for next state logic for outputs inputs outputs state feedback reg combinational logic for next state logic for outputs CS 150 - Fall 2000 - Introduction - 90

Mealy and Moore Examples Recognize A,B = 0,1 Mealy or Moore? CS 150 - Fall 2000 - Introduction - 91

Mealy and Moore Examples (cont’d) Recognize A,B = 1,0 then 0,1 Mealy or Moore? CS 150 - Fall 2000 - Introduction - 92

Registered Mealy Machine (Really Moore) Synchronous (or registered) Mealy Machine Registered state AND outputs Avoids ‘glitchy’ outputs Easy to implement in PLDs Moore Machine with no output decoding Outputs computed on transition to next state rather than after entering View outputs as expanded state vector output logic Outputs Inputs next state logic CS 150 - Fall 2000 - Introduction - 93 Current State

Example: Vending Machine Release item after 15 cents are deposited Single coin slot for dimes, nickels No change Reset N Vending Machine FSM Open Coin Sensor Release Mechanism D Clock CS 150 - Fall 2000 - Introduction - 94

Example: Vending Machine (cont’d) Suitable Abstract Representation Tabulate typical input sequences: 3 nickels nickel, dime dime, nickel two dimes Draw state diagram: Inputs: N, D, reset Output: open chute Assumptions: Assume N and D asserted for one cycle Each state has a self loop for N = D = 0 (no coin) S0 Reset S1 N S2 D S3 N S4 [open] D S5 [open] N S6 [open] D S7 [open] N CS 150 - Fall 2000 - Introduction - 95

Example: Vending Machine (cont’d) Minimize number of states - reuse states whenever possible 0¢ Reset symbolic state table present inputs next output state D N state open 0¢ 0 0 0¢ 0 0 1 5¢ 0 1 0 10¢ 0 1 1 – – 5¢ 0 0 5¢ 0 0 1 10¢ 0 1 0 15¢ 0 1 1 – – 10¢ 0 0 10¢ 0 0 1 15¢ 0 1 0 15¢ 0 1 1 – – 15¢ – – 15¢ 1 10¢ D 5¢ N 15¢ [open] D N N + D CS 150 - Fall 2000 - Introduction - 96

Example: Vending Machine (cont’d) Uniquely Encode States present state inputs next state output Q1 Q0 D N D1 D0 open 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 – – – 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 – – – 1 0 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 1 1 – – – 1 1 – – 1 1 1 CS 150 - Fall 2000 - Introduction - 97

Example: Vending Machine (cont’d) Mapping to Logic 0 0 1 1 0 1 1 1 X X X X 1 1 1 1 Q1 D1 Q0 N D 0 1 1 0 1 0 1 1 D0 0 0 1 0 Open D1 = Q1 + D + Q0 N D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D OPEN = Q1 Q0 CS 150 - Fall 2000 - Introduction - 98

Example: Vending Machine (cont’d) One-hot Encoding present state inputs next state output Q3 Q2 Q1 Q0 D N D3 D2 D1 D0 open 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 - - - - - 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 1 - - - - - 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 - - - - - 1 0 0 0 - - 1 0 0 0 1 D0 = Q0 D’ N’ D1 = Q0 N + Q1 D’ N’ D2 = Q0 D + Q1 N + Q2 D’ N’ D3 = Q1 D + Q2 D + Q2 N + Q3 OPEN = Q3 CS 150 - Fall 2000 - Introduction - 99

Equivalent Mealy and Moore State Diagrams Moore machine outputs associated with state Mealy machine outputs associated with transitions 0¢ [0] 10¢ 5¢ 15¢ [1] N’ D’ + Reset D N N+D N’ D’ Reset’ Reset 0¢ 10¢ 5¢ 15¢ (N’ D’ + Reset)/0 D/0 D/1 N/0 N+D/1 N’ D’/0 Reset’/1 Reset/0 CS 150 - Fall 2000 - Introduction - 100

Example: Traffic Light Controller A busy highway is intersected by a little used farmroad Detectors C sense the presence of cars waiting on the farmroad with no car on farmroad, light remain green in highway direction if vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green these stay green only as long as a farmroad car is detected but never longer than a set interval when these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green even if farmroad vehicles are waiting, highway gets at least a set interval as green Assume you have an interval timer that generates: a short time pulse (TS) and a long time pulse (TL), in response to a set (ST) signal. TS is to be used for timing yellow lights and TL for green lights CS 150 - Fall 2000 - Introduction - 101

Example: Traffic Light Controller (cont’) Highway/farm road intersection farm road car sensors highway CS 150 - Fall 2000 - Introduction - 102

Example: Traffic Light Controller (cont’) Tabulation of Inputs and Outputs inputs description outputs description reset place FSM in initial state HG, HY, HR assert green/yellow/red highway lights C detect vehicle on the farm road FG, FY, FR assert green/yellow/red highway lights TS short time interval expired ST start timing a short or long interval TL long time interval expired Tabulation of unique states – some light configurations imply others state description S0 highway green (farm road red) S1 highway yellow (farm road red) S2 farm road green (highway red) S3 farm road yellow (highway red) CS 150 - Fall 2000 - Introduction - 103

Example: Traffic Light Controller (cont’) State Diagram Reset TS' TS / ST (TL•C)' TL•C / ST (TL+C')' TL+C' / ST S0 S2 S3 S1 S0: HG S1: HY S2: FG S3: FY CS 150 - Fall 2000 - Introduction - 104

Example: Traffic Light Controller (cont’) Generate state table with symbolic states Consider state assignments output encoding – similar problem to state assignment (Green = 00, Yellow = 01, Red = 10) Inputs Present State Next State Outputs C TL TS ST H F 0 – – HG HG 0 Green Red – 0 – HG HG 0 Green Red 1 1 – HG HY 1 Green Red – – 0 HY HY 0 Yellow Red – – 1 HY FG 1 Yellow Red 1 0 – FG FG 0 Red Green 0 – – FG FY 1 Red Green – 1 – FG FY 1 Red Green – – 0 FY FY 0 Red Yellow – – 1 FY HG 1 Red Yellow SA1: HG = 00 HY = 01 FG = 11 FY = 10 SA2: HG = 00 HY = 10 FG = 01 FY = 11 SA3: HG = 0001 HY = 0010 FG = 0100 FY = 1000 (one-hot) CS 150 - Fall 2000 - Introduction - 105

Logic for Different State Assignments SA1 NS1 = C•TL'•PS1•PS0 + TS•PS1'•PS0 + TS•PS1•PS0' + C'•PS1•PS0 + TL•PS1•PS0 NS0 = C•TL•PS1'•PS0' + C•TL'•PS1•PS0 + PS1'•PS0 ST = C•TL•PS1'•PS0' + TS•PS1'•PS0 + TS•PS1•PS0' + C'•PS1•PS0 + TL•PS1•PS0 H1 = PS1 H0 = PS1'•PS0 F1 = PS1' F0 = PS1•PS0' SA2 NS1 = C•TL•PS1' + TS'•PS1 + C'•PS1'•PS0 NS0 = TS•PS1•PS0' + PS1'•PS0 + TS'•PS1•PS0 ST = C•TL•PS1' + C'•PS1'•PS0 + TS•PS1 H1 = PS0 H0 = PS1•PS0' F1 = PS0' F0 = PS1•PS0 SA3 NS3 = C'•PS2 + TL•PS2 + TS'•PS3 NS2 = TS•PS1 + C•TL'•PS2 NS1 = C•TL•PS0 + TS'•PS1 NS0 = C'•PS0 + TL'•PS0 + TS•PS3 ST = C•TL•PS0 + TS•PS1 + C'•PS2 + TL•PS2 + TS•PS3 H1 = PS3 + PS2 H0 = PS1 F1 = PS1 + PS0 F0 = PS3 CS 150 - Fall 2000 - Introduction - 106

Vending Machine Example (PLD mapping) D0 = reset'(Q0'N + Q0N' + Q1N + Q1D) D1 = reset'(Q1 + D + Q0N) OPEN = Q1Q0 D Q Q0 Q1 Open Com Seq CLK N Reset CS 150 - Fall 2000 - Introduction - 107

Vending Machine (cont’d) OPEN = Q1Q0 creates a combinational delay after Q1 and Q0 change This can be corrected by retiming, i.e., move flip-flops and logic through each other to improve delay OPEN = reset'(Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D) = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D) Implementation now looks like a synchronous Mealy machine Common for programmable devices to have FF at end of logic CS 150 - Fall 2000 - Introduction - 108

Vending Machine (Retimed PLD Mapping) OPEN = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D) OPEN D Q Q0 Q1 Open Seq CLK N Reset CS 150 - Fall 2000 - Introduction - 109

Finite State Machine Optimization Should look over this one Make sure you know the motivation for this State Minimization Try to merge state with same behavior so total # of states are less State Encoding Less combinational logic involved in implementing if correct state encoding is chosen. Less Flip flops used if a more dense encoding is used. # of flip flop could range from log2(n) to n Make sure you know the algorithm for both CS 150 - Fall 2000 - Introduction - 110

Finite State Machine Optimization State Minimization Fewer states require fewer state bits Fewer bits require fewer logic equations Encodings: State, Inputs, Outputs State encoding with fewer bits has fewer equations to implement However, each may be more complex State encoding with more bits (e.g., one-hot) has simpler equations Complexity directly related to complexity of state diagram Input/output encoding may or may not be under designer control CS 150 - Fall 2000 - Introduction - 111

Algorithmic Approach to State Minimization Goal – identify and combine states that have equivalent behavior Equivalent States: Same output For all input combinations, states transition to same or equivalent states Algorithm Sketch 1. Place all states in one set 2. Initially partition set based on output behavior 3. Successively partition resulting subsets based on next state transitions 4. Repeat (3) until no further partitioning is required states left in the same set are equivalent Polynomial time procedure CS 150 - Fall 2000 - Introduction - 112

State Minimization Example Sequence Detector for 010 or 110 Input Next State Output Sequence Present State X=0 X=1 X=0 X=1 Reset S0 S1 S2 0 0 0 S1 S3 S4 0 0 1 S2 S5 S6 0 0 00 S3 S0 S0 0 0 01 S4 S0 S0 1 0 10 S5 S0 S0 0 0 11 S6 S0 S0 1 0 S0 S3 S2 S1 S5 S6 S4 1/0 0/0 0/1 CS 150 - Fall 2000 - Introduction - 113

Method of Successive Partitions Input Next State Output Sequence Present State X=0 X=1 X=0 X=1 Reset S0 S1 S2 0 0 0 S1 S3 S4 0 0 1 S2 S5 S6 0 0 00 S3 S0 S0 0 0 01 S4 S0 S0 1 0 10 S5 S0 S0 0 0 11 S6 S0 S0 1 0 ( S0 S1 S2 S3 S4 S5 S6 ) ( S0 S1 S2 S3 S5 ) ( S4 S6 ) ( S0 S3 S5 ) ( S1 S2 ) ( S4 S6 ) ( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 ) S1 is equivalent to S2 S3 is equivalent to S5 S4 is equivalent to S6 CS 150 - Fall 2000 - Introduction - 114

CS 150 - Fall 2000 - Introduction - 115 Minimized FSM State minimized sequence detector for 010 or 110 Input Next State Output Sequence Present State X=0 X=1 X=0 X=1 Reset S0 S1' S1' 0 0 0 + 1 S1' S3' S4' 0 0 X0 S3' S0 S0 0 0 X1 S4' S0 S0 1 0 S0 S1’ S3’ S4’ X/0 1/0 0/1 0/0 CS 150 - Fall 2000 - Introduction - 115

More Complex State Minimization Multiple input example inputs here 10 01 11 00 S0 [1] S2 [1] S4 [1] S1 [0] S3 S5 present next state output state 00 01 10 11 S0 S0 S1 S2 S3 1 S1 S0 S3 S1 S4 0 S2 S1 S3 S2 S4 1 S3 S1 S0 S4 S5 0 S4 S0 S1 S2 S5 1 S5 S1 S4 S0 S5 0 symbolic state transition table CS 150 - Fall 2000 - Introduction - 116

CS 150 - Fall 2000 - Introduction - 117 Minimized FSM Implication Chart Method Cross out incompatible states based on outputs Then cross out more cells if indexed chart entries are already crossed out S1 S2 S3 S4 S5 S0 minimized state table (S0==S4) (S3==S5) present next state output state 00 01 10 11 S0' S0' S1 S2 S3' 1 S1 S0' S3' S1 S3' 0 S2 S1 S3' S2 S0' 1 S3' S1 S0' S0' S3' 0 S0-S1 S1-S3 S2-S2 S3-S4 S0-S1 S3-S0 S1-S4 S4-S5 S0-S0 S1-S1 S2-S2 S3-S5 S1-S0 S3-S1 S2-S2 S4-S5 S0-S1 S3-S4 S1-S0 S4-S5 S4-S0 S5-S5 S1-S1 S0-S4 CS 150 - Fall 2000 - Introduction - 117

Minimizing Incompletely Specified FSMs Equivalence of states is transitive when machine is fully specified But its not transitive when don't cares are present e.g., state output S0 – 0 S1 is compatible with both S0 and S2 S1 1 – but S0 and S2 are incompatible S2 – 1 No polynomial time algorithm exists for determining best grouping of states into equivalent sets that will yield the smallest number of final states CS 150 - Fall 2000 - Introduction - 118

Minimizing States May Not Yield Best Circuit Example: edge detector - outputs 1 when last two input changes from 0 to 1 X Q1 Q0 Q1+ Q0+ 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 – 1 0 0 0 00 [0] 11 [0] 01 [1] X’ X Q1+ = X (Q1 xor Q0) Q0+ = X Q1’ Q0’ CS 150 - Fall 2000 - Introduction - 119

Another Implementation of Edge Detector "Ad hoc" solution - not minimal but cheap and fast 00 [0] 10 [0] 01 [1] X’ X 11 [0] CS 150 - Fall 2000 - Introduction - 120

CS 150 - Fall 2000 - Introduction - 121 State Assignment Choose bit vectors to assign to each “symbolic” state With n state bits for m states there are 2n! / (2n – m)! [log n <= m <= 2n] 2n codes possible for 1st state, 2n–1 for 2nd, 2n–2 for 3rd, … Huge number even for small values of n and m Intractable for state machines of any size Heuristics are necessary for practical solutions Optimize some metric for the combinational logic Size (amount of logic and number of FFs) Speed (depth of logic and fanout) Dependencies (decomposition) CS 150 - Fall 2000 - Introduction - 121

State Assignment Strategies Possible Strategies Sequential – just number states as they appear in the state table Random – pick random codes One-hot – use as many state bits as there are states (bit=1 –> state) Output – use outputs to help encode states Heuristic – rules of thumb that seem to work in most cases No guarantee of optimality – another intractable problem CS 150 - Fall 2000 - Introduction - 122

One-hot State Assignment Simple Easy to encode, debug Small Logic Functions Each state function requires only predecessor state bits as input Good for Programmable Devices Lots of flip-flops readily available Simple functions with small support (signals its dependent upon) Impractical for Large Machines Too many states require too many flip-flops Decompose FSMs into smaller pieces that can be one-hot encoded Many Slight Variations to One-hot One-hot + all-0 CS 150 - Fall 2000 - Introduction - 123

Heuristics for State Assignment Adjacent codes to states that share a common next state Group 1's in next state map Adjacent codes to states that share a common ancestor state Adjacent codes to states that have a common output behavior Group 1's in output map i / j i / k a b c I Q Q+ O i a c j i b c k c = i * a + i * b a b c i / j k / l I Q Q+ O i a b j k a c l b = i * a c = k * a I Q Q+ O i a b j i c d j j = i * a + i * c b = i * a d = i * c b d i / j a c CS 150 - Fall 2000 - Introduction - 124

General Approach to Heuristic State Assignment All current methods are variants of this 1) Determine which states “attract” each other (weighted pairs) 2) Generate constraints on codes (which should be in same cube) 3) Place codes on Boolean cube so as to maximize constraints satisfied (weighted sum) Different weights make sense depending on whether we are optimizing for two-level or multi-level forms Can't consider all possible embeddings of state clusters in Boolean cube Heuristics for ordering embedding To prune search for best embedding Expand cube (more state bits) to satisfy more constraints CS 150 - Fall 2000 - Introduction - 125

Output-Based Encoding Reuse outputs as state bits - use outputs to help distinguish states Why create new functions for state bits when output can serve as well Fits in nicely with synchronous Mealy implementations Inputs Present State Next State Outputs C TL TS ST H F 0 – – HG HG 0 00 10 – 0 – HG HG 0 00 10 1 1 – HG HY 1 00 10 – – 0 HY HY 0 01 10 – – 1 HY FG 1 01 10 1 0 – FG FG 0 10 00 0 – – FG FY 1 10 00 – 1 – FG FY 1 10 00 – – 0 FY FY 0 10 01 – – 1 FY HG 1 10 01 HG = ST’ H1’ H0’ F1 F0’ + ST H1 H0’ F1’ F0 HY = ST H1’ H0’ F1 F0’ + ST’ H1’ H0 F1 F0’ FG = ST H1’ H0 F1 F0’ + ST’ H1 H0’ F1’ F0’ HY = ST H1 H0’ F1’ F0’ + ST’ H1 H0’ F1’ F0 Output patterns are unique to states, we do not need ANY state bits – implement 5 functions (one for each output) instead of 7 (outputs plus 2 state bits) CS 150 - Fall 2000 - Introduction - 126

Current State Assignment Approaches For tight encodings using close to the minimum number of state bits Best of 10 random seems to be adequate (averages as well as heuristics) Heuristic approaches are not even close to optimality Used in custom chip design One-hot encoding Easy for small state machines Generates small equations with easy to estimate complexity Common in FPGAs and other programmable logic Output-based encoding Ad hoc - no tools Most common approach taken by human designers Yields very small circuits for most FSMs CS 150 - Fall 2000 - Introduction - 127

Sequential Logic Implementation Summary Models for representing sequential circuits Abstraction of sequential elements Finite state machines and their state diagrams Inputs/outputs Mealy, Moore, and synchronous Mealy machines Finite state machine design procedure Deriving state diagram Deriving state transition table Determining next state and output functions Implementing combinational logic Implementation of sequential logic State minimization State assignment Support in programmable logic devices CS 150 - Fall 2000 - Introduction - 128

Sequential Logic Examples Finite State Machine Concept FSMs are the decision making logic of digital designs Partitioning designs into datapath and control elements When inputs are sampled and outputs asserted Basic Design Approach: 4-step Design Process Implementation Examples and Case Studies Finite-string pattern recognizer Complex counter Traffic light controller Door combination lock CS 150 - Fall 2000 - Introduction - 129

General FSM Design Procedure (1) Determine inputs and outputs (2) Determine possible states of machine – State minimization (3) Encode states and outputs into a binary code – State assignment or state encoding – Output encoding – Possibly input encoding (if under our control) (4) Realize logic to implement functions for states and outputs – Combinational logic implementation and optimization – Choices in steps 2 and 3 have large effect on resulting logic CS 150 - Fall 2000 - Introduction - 130

Finite String Pattern Recognizer (Step 1) One input (X) and one output (Z) Output is asserted whenever the input sequence …010… has been observed, as long as the sequence 100 has never been seen Step 1: Understanding the Problem Statement Sample input/output behavior: X: 0 0 1 0 1 0 1 0 0 1 0 … Z: 0 0 0 1 0 1 0 1 0 0 0 … X: 1 1 0 1 1 0 1 0 0 1 0 … Z: 0 0 0 0 0 0 0 1 0 0 0 … CS 150 - Fall 2000 - Introduction - 131

Finite String Pattern Recognizer (Step 2) Step 2: Draw State Diagram For the strings that must be recognized, i.e., 010 and 100 Moore implementation S0 [0] reset S1 [0] S2 1 S3 [1] S4 [0] 1 0 or 1 S5 [0] S6 [0] CS 150 - Fall 2000 - Introduction - 132

Finite String Pattern Recognizer (Step 2, cont’d) Exit conditions from state S3: have recognized …010 If next input is 0 then have …0100 = ...100 (state S6) If next input is 1 then have …0101 = …01 (state S2) 1 ...01 ...010 ...100 S4 [0] S1 [0] S0 [0] S2 reset 0 or 1 S3 [1] S5 [0] S6 [0] Exit conditions from S1: recognizes strings of form …0 (no 1 seen); loop back to S1 if input is 0 Exit conditions from S4: recognizes strings of form …1 (no 0 seen); loop back to S4 if input is 1 ...1 ...0 1 CS 150 - Fall 2000 - Introduction - 133

Finite String Pattern Recognizer (Step 2, cont’d) S2 and S5 still have incomplete transitions S2 = …01; If next input is 1, then string could be prefix of (01)1(00) S4 handles just this case S5 = …10; If next input is 1, then string could be prefix of (10)1(0) S2 handles just this case Reuse states as much as possible Look for same meaning State minimization leads to smaller number of bits to represent states Once all states have complete set of transitions we have final state diagram 1 ...01 ...010 ...100 S4 [0] S1 [0] S0 [0] S2 reset 0 or 1 S3 [1] S5 [0] S6 [0] ...1 ...0 1 ...10 1 CS 150 - Fall 2000 - Introduction - 134

Finite String Pattern Recognizer Review of Process Understanding problem Write down sample inputs and outputs to understand specification Derive a state diagram Write down sequences of states and transitions for sequences to be recognized Minimize number of states Add missing transitions; reuse states as much as possible State assignment or encoding Encode states with unique patterns Simulate realization Verify I/O behavior of your state diagram to ensure it matches specification CS 150 - Fall 2000 - Introduction - 135

CS 150 - Fall 2000 - Introduction - 136 Complex Counter Synchronous 3-bit counter has a mode control M When M = 0, the counter counts up in the binary sequence When M = 1, the counter advances through the Gray code sequence binary: 000, 001, 010, 011, 100, 101, 110, 111 Gray: 000, 001, 011, 010, 110, 111, 101, 100 Valid I/O behavior (partial) Mode Input M 1 Current State 000 001 010 110 111 101 Next State CS 150 - Fall 2000 - Introduction - 136

Complex Counter (State Diagram) Deriving State Diagram One state for each output combination Add appropriate arcs for the mode control S0 [000] S1 [001] S2 [010] S3 [011] S4 [100] S5 [101] S6 [110] S7 [111] reset 1 CS 150 - Fall 2000 - Introduction - 137

Traffic Light Controller as Two Communicating FSMs Without Separate Timer S0 would require 7 states S1 would require 3 states S2 would require 7 states S3 would require 3 states S1 and S3 have simple transformation S0 and S2 would require many more arcs C could change in any of seven states By Factoring Out Timer Greatly reduce number of states 4 instead of 20 Counter only requires seven or eight states 12 total instead of 20 TS/ST S1 TS' –/ST S1a S1b S1c traffic light controller ST TS TL timer CS 150 - Fall 2000 - Introduction - 138

Communicating Finite State Machines One machine's output is another machine's input FSM 1 FSM 2 X Y CLK FSM1 X FSM2 Y A B C D Y==1 A [1] Y==0 B [0] X==1 C [0] X==0 D [1] machines advance in lock step initial inputs/outputs: X = 0, Y = 0 CS 150 - Fall 2000 - Introduction - 139

Datapath and Control Digital hardware systems = data-path + control Datapath: registers, counters, combinational functional units (e.g., ALU), communication (e.g., busses) Control: FSM generating sequences of control signals that instructs datapath what to do next "puppeteer who pulls the strings" control status info and inputs control signal outputs state data-path "puppet" CS 150 - Fall 2000 - Introduction - 140

Digital Combinational Lock Door Combination Lock: Punch in 3 values in sequence and the door opens; if there is an error the lock must be reset; once the door opens the lock must be reset Inputs: sequence of input values, reset Outputs: door open/close Memory: must remember combination or always have it available Open questions: how do you set the internal combination? Stored in registers (how loaded?) Hardwired via switches set by user CS 150 - Fall 2000 - Introduction - 141

Determining Details of the Specification How many bits per input value? How many values in sequence? How do we know a new input value is entered? What are the states and state transitions of the system? reset value open/closed new clock CS 150 - Fall 2000 - Introduction - 142

Digital Combination Lock State Diagram States: 5 states Represent point in execution of machine Each state has outputs Transitions: 6 from state to state, 5 self transitions, 1 global Changes of state occur when clock says its ok Based on value of inputs Inputs: reset, new, results of comparisons Output: open/closed ERR closed C1!=value & new C2!=value & new C3!=value & new S1 S2 S3 OPEN reset closed closed closed open C1==value & new C2==value & new C3==value & new CS 150 - Fall 2000 - Introduction - 143 not new not new not new

Datapath and Control Structure Storage registers for combination values Multiplexer Comparator Control Finite-state machine controller Control for data-path (which value to compare) reset open/closed new C1 C2 C3 comparator value equal multiplexer controller mux control clock 4 CS 150 - Fall 2000 - Introduction - 144

State Table for Combination Lock Finite-State Machine Refine state diagram to take internal structure into account State table ready for encoding reset new equal state state mux open/closed 1 – – – S1 C1 closed 0 0 – S1 S1 C1 closed 0 1 0 S1 ERR – closed 0 1 1 S1 S2 C2 closed ... 0 1 1 S3 OPEN – open ... next CS 150 - Fall 2000 - Introduction - 145

Encodings for Combination Lock Encode state table State can be: S1, S2, S3, OPEN, or ERR Needs at least 3 bits to encode: 000, 001, 010, 011, 100 And as many as 5: 00001, 00010, 00100, 01000, 10000 Choose 4 bits: 0001, 0010, 0100, 1000, 0000 Output mux can be: C1, C2, or C3 Needs 2 to 3 bits to encode Choose 3 bits: 001, 010, 100 Output open/closed can be: open or closed Needs 1 or 2 bits to encode Choose 1 bit: 1, 0 reset open/closed new equal controller mux control clock reset new equal state state mux open/closed 1 – – – 0001 001 0 0 0 – 0001 0001 001 0 0 1 0 0001 0000 – 0 0 1 1 0001 0010 010 0 ... 0 1 1 0100 1000 – 1 ... next mux is identical to last 3 bits of state open/closed is identical to first bit of state therefore, we do not even need to implement FFs to hold state, just use outputs CS 150 - Fall 2000 - Introduction - 146

Datapath Implementation for Combination Lock Multiplexer Easy to implement as combinational logic when few inputs Logic can easily get too big for most PLDs C1i C2i C3i mux control value equal C1 C2 C3 comparator equal multiplexer mux control 4 value CS 150 - Fall 2000 - Introduction - 147

Datapath Implementation (cont’d) Tri-State Logic Utilize a third output state: “no connection” or “float” Connect outputs together as long as only one is “enabled” Open-collector gates can only output 0, not 1 Can be used to implement logical AND with only wires C1i C2i C3i mux control value equal + oc C1 C2 C3 comparator equal multiplexer mux control 4 value tri-state driver (can disconnect from output) open-collector connection (zero whenever one connection is zero, one otherwise – wired AND) CS 150 - Fall 2000 - Introduction - 148

CS 150 - Fall 2000 - Introduction - 149 Tri-states Very important in real life Probably not as important on the test… You should know how they work by now anyways. CS 150 - Fall 2000 - Introduction - 149

CS 150 - Fall 2000 - Introduction - 150 Tri-State Gates Third value Logic values: “0”, “1” Don't care: “X” (must be 0 or 1 in real circuit!) Third value or state: “Z” — high impedance, infinite R, no connection Tri-state gates Additional input – output enable (OE) Output values are 0, 1, and Z When OE is high, the gate functions normally When OE is low, the gate is disconnected from wire at output Allows more than one gate to be connected to the same output wire As long as only one has its output enabled at any one time (otherwise, sparks could fly) OE In Out 100 In OE Out X 0 Z 0 1 0 1 1 1 non-inverting tri-state buffer In OE Out CS 150 - Fall 2000 - Introduction - 150

Tri-State and Multiplexing When Using Tri-State Logic (1) Never more than one "driver" for a wire at any one time (pulling high and low at same time can severely damage circuits) (2) Only use value on wire when its being driven (using a floating value may cause failures) Using Tri-State Gates to Implement an Economical Multiplexer OE F Input0 Input1 Select when Select is high Input1 is connected to F when Select is low Input0 is connected to F this is essentially a 2:1 mux CS 150 - Fall 2000 - Introduction - 151

Open-Collector Gates and Wired-AND Um… I didn’t know what they were, and had to ask prof. Katz after class Not too important. CS 150 - Fall 2000 - Introduction - 152

Open-Collector Gates and Wired-AND Open collector: another way to connect gate outputs to same wire Gate only has the ability to pull its output low Cannot actively drive wire high (default – pulled high through resistor) Wired-AND can be implemented with open collector logic If A and B are "1", output is actively pulled low If C and D are "1", output is actively pulled low If one gate output is low and the other high, then low wins If both outputs are "1", the wire value "floats", pulled high by resistor Low to high transition usually slower than if gate pulling high Hence, the two NAND functions are ANDed together with ouputs wired together using "wired-AND" to form (AB)'(CD)' open-collector NAND gates CS 150 - Fall 2000 - Introduction - 153

Digital Combination Lock (New Datapath) Decrease number of inputs Remove 3 code digits as inputs Use code registers Make them loadable from value Need 3 load signal inputs (net gain in input (4*3)–3=9) Could be done with 2 signals and decoder (ld1, ld2, ld3, load none) C1 C2 C3 comparator value equal multiplexer mux control 4 ld1 ld2 ld3 CS 150 - Fall 2000 - Introduction - 154

CS 150 - Fall 2000 - Introduction - 155 Section Summary FSM Design Understanding the problem Generating state diagram Implementation using synthesis tools Iteration on design/specification to improve qualities of mapping Communicating state machines Four case studies Understand I/O behavior Draw diagrams Enumerate states for the "goal" Expand with error conditions Reuse states whenever possible CS 150 - Fall 2000 - Introduction - 155

Computer Organization Computer design as an application of digital logic design procedures Computer = processing unit + memory system Processing unit = control + datapath Control = finite state machine Inputs = machine instruction, datapath conditions Outputs = register transfer control signals, ALU operation codes Instruction interpretation = instruction fetch, decode, execute Datapath = functional units + registers Functional units = ALU, multipliers, dividers, etc. Registers = program counter, shifters, storage registers CS 150 - Fall 2000 - Introduction - 156

Structure of a Computer Block diagram view control signals data conditions Data Path Control address read/write data Processor Memory System central processing unit (CPU) instruction unit – instruction fetch and interpretation FSM execution unit – functional units and registers CS 150 - Fall 2000 - Introduction - 157

Registers Selectively loaded – EN or LD input Output enable – OE input Multiple registers – group 4 or 8 in parallel OE Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 LD D7 D6 D5 D4 D3 D2 D1 D0 CLK OE asserted causes FF state to be connected to output pins; otherwise they are left unconnected (high impedance) LD asserted during a lo-to-hi clock transition loads new data into FFs CS 150 - Fall 2000 - Introduction - 158

CS 150 - Fall 2000 - Introduction - 159 Register Transfer rt MUX rs rd R4 Point-to-point connection Dedicated wires Muxes on inputs of each register Common input from multiplexer Load enables for each register Control signals for multiplexer Common bus with output enables Output enables and load enables for each register rs MUX rt rd R4 BUS rs rt rd R4 CS 150 - Fall 2000 - Introduction - 159

CS 150 - Fall 2000 - Introduction - 160 Register Files Collections of registers in one package Two-dimensional array of FFs Address used as index to a particular word Separate read and write addresses so can do both at same time 4 by 4 register file 16 D-FFs Organized as four words of four bits each Write-enable (load) Read-enable (output enable) RE RB RA WE WB WA D3 D2 D1 D0 Q3 Q2 Q1 Q0 CS 150 - Fall 2000 - Introduction - 160

CS 150 - Fall 2000 - Introduction - 161 Memories Larger Collections of Storage Elements Implemented not as FFs but as much more efficient latches High-density memories use 1-5 switches (transitors) per bit Static RAM – 1024 words each 4 bits wide Once written, memory holds forever (not true for denser dynamic RAM) Address lines to select word (10 lines for 1024 words) Read enable Same as output enable Often called chip select Permits connection of many chips into larger array Write enable (same as load enable) Bi-directional data lines output when reading, input when writing RD WR A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 IO3 IO2 IO1 IO0 CS 150 - Fall 2000 - Introduction - 161

The rest is probably not too important for the test Although it is a cool topic Computer Architecture is fun, really Make sure you understand the REGISTER FILE and MEMORY form the few slides before this one though. CS 150 - Fall 2000 - Introduction - 162

Instruction Sequencing Example – an instruction to add the contents of two registers (Rx and Ry) and place result in a third register (Rz) Step 1: Get the ADD instruction from memory into an instruction register Step 2: Decode instruction Instruction in IR has the code of an ADD instruction Register indices used to generate output enables for registers Rx and Ry Register index used to generate load signal for register Rz Step 3: execute instruction Enable Rx and Ry output and direct to ALU Setup ALU to perform ADD operation Direct result to Rz so that it can be loaded into register CS 150 - Fall 2000 - Introduction - 163

CS 150 - Fall 2000 - Introduction - 164 Instruction Types Data Manipulation Add, subtract Increment, decrement Multiply Shift, rotate Immediate operands Data Staging Load/store data to/from memory Register-to-register move Control Conditional/unconditional branches in program flow Subroutine call and return CS 150 - Fall 2000 - Introduction - 164

Elements of the Control Unit (aka Instruction Unit) Standard FSM Elements State register Next-state logic Output logic (datapath/control signalling) Moore or synchronous Mealy machine to avoid loops unbroken by FF Plus Additional ”Control" Registers Instruction register (IR) Program counter (PC) Inputs/Outputs Outputs control elements of data path Inputs from data path used to alter flow of program (test if zero) CS 150 - Fall 2000 - Introduction - 165

Instruction Execution Control State Diagram (for each diagram) Reset Fetch instruction Decode Execute Instructions partitioned into three classes Branch Load/store Register-to-register Different sequence through diagram for each instruction type Reset Init Initialize Machine Fetch Instr. Load/ Store XEQ Instr. Branch Register- to-Register Branch Taken Branch Not Taken Incr. PC CS 150 - Fall 2000 - Introduction - 166

CS 150 - Fall 2000 - Introduction - 167 Data Path (Hierarchy) Arithmetic circuits constructed in hierarchical and iterative fashion each bit in datapath is functionally identical 4-bit, 8-bit, 16-bit, 32-bit datapaths Cin Ain Bin Sum Cout FA HA CS 150 - Fall 2000 - Introduction - 167

CS 150 - Fall 2000 - Introduction - 168 Data Path (ALU) ALU Block Diagram Input: data and operation to perform Output: result of operation and status information 16 A B S Z N Operation CS 150 - Fall 2000 - Introduction - 168

Data Path (ALU + Registers) Accumulator Special register One of the inputs to ALU Output of ALU stored back in accumulator One-address instructions Operation and address of one operand Other operand and destination is accumulator register AC <– AC op Mem[addr] ”Single address instructions” (AC implicit operand) Multiple registers Part of instruction used to choose register operands 16 Z N OP AC REG CS 150 - Fall 2000 - Introduction - 169

CS 150 - Fall 2000 - Introduction - 170 Data Path (Bit-slice) Bit-slice concept: iterate to build n-bit wide datapaths CO CI ALU AC R0 from memory rs rt rd CO ALU AC R0 from memory rs rt rd CI 1 bit wide 2 bits wide CS 150 - Fall 2000 - Introduction - 170

CS 150 - Fall 2000 - Introduction - 171 Instruction Path Program Counter Keeps track of program execution Address of next instruction to read from memory May have auto-increment feature or use ALU Instruction Register Current instruction Includes ALU operation and address of operand Also holds target of jump instruction Immediate operands Relationship to Data Path PC may be incremented through ALU Contents of IR may also be required as input to ALU CS 150 - Fall 2000 - Introduction - 171

Data Path (Memory Interface) Separate data and instruction memory (Harvard architecture) Two address busses, two data busses Single combined memory (Princeton architecture) Single address bus, single data bus Separate memory ALU output goes to data memory input Register input from data memory output Data memory address from instruction register Instruction register from instruction memory output Instruction memory address from program counter Single memory Address from PC or IR Memory output to instruction and data registers Memory input from ALU output CS 150 - Fall 2000 - Introduction - 172

Block Diagram of Processor Register Transfer View of Princeton Architecture Which register outputs are connected to which register inputs Arrows represent data-flow, other are control signals from control FSM MAR may be a simple multiplexer rather than separate register MBR is split in two (REG and IR) Load control for each register load path 16 REG AC rd wr 16 16 store path data Data Memory (16-bit words) OP N addr 8 Z Control FSM MAR 16 IR PC 16 16 OP 16 CS 150 - Fall 2000 - Introduction - 173

Block Diagram of Processor Register transfer view of Harvard architecture Which register outputs are connected to which register inputs Arrows represent data-flow, other are control signals from control FSM Two MARs (PC and IR) Two MBRs (REG and IR) Load control for each register Control FSM 16 Z N OP AC REG load path store path Data Memory (16-bit words) PC IR data addr rd wr Inst Memory (8-bit words) CS 150 - Fall 2000 - Introduction - 174

A simplified Processor Data-path and Memory Princeton architecture Register file Instruction register PC incremented through ALU Modeled after MIPS rt000 (used in 378 textbook by Patterson & Hennessy) Really a 32 bit machine We’ll do a 16 bit version memory has only 255 words with a display on the last one CS 150 - Fall 2000 - Introduction - 175

CS 150 - Fall 2000 - Introduction - 176 Processor Control Synchronous Mealy machine Multiple cycles per instruction CS 150 - Fall 2000 - Introduction - 176

Processor Instructions Three principal types (16 bits in each instruction) type op rs rt rd funct R(egister) 3 3 3 3 4 I(mmediate) 3 3 3 7 J(ump) 3 13 Some of the instructions add 0 rs rt rd 0 rd = rs + rt sub 0 rs rt rd 1 rd = rs - rt and 0 rs rt rd 2 rd = rs & rt or 0 rs rt rd 3 rd = rs | rt slt 0 rs rt rd 4 rd = (rs < rt) lw 1 rs rt offset rt = mem[rs + offset] sw 2 rs rt offset mem[rs + offset] = rt beq 3 rs rt offset pc = pc + offset, if (rs == rt) addi 4 rs rt offset rt = rs + offset j 5 target address pc = target address halt 7 - stop execution until reset R I J CS 150 - Fall 2000 - Introduction - 177

Tracing an Instruction's Execution Instruction: r3 = r1 + r2 R 0 rs=r1 rt=r2 rd=r3 funct=0 1. Instruction fetch Move instruction address from PC to memory address bus Assert memory read Move data from memory data bus into IR Configure ALU to add 1 to PC Configure PC to store new value from ALUout 2. Instruction decode Op-code bits of IR are input to control FSM Rest of IR bits encode the operand addresses (rs and rt) These go to register file CS 150 - Fall 2000 - Introduction - 178

Tracing an Instruction's Execution (cont’d) Instruction: r3 = r1 + r2 R 0 rs=r1 rt=r2 rd=r3 funct=0 3. Instruction execute Set up ALU inputs Configure ALU to perform ADD operation Configure register file to store ALU result (rd) CS 150 - Fall 2000 - Introduction - 179

Tracing an Instruction's Execution (cont’d) Step 1 CS 150 - Fall 2000 - Introduction - 180

Tracing an Instruction's Execution (cont’d) Step 2 to controller CS 150 - Fall 2000 - Introduction - 181

Tracing an Instruction's Execution (cont’d) Step 3 CS 150 - Fall 2000 - Introduction - 182

Register-Transfer-Level Description Control Transfer data btwn registers by asserting appropriate control signals Register transfer notation: work from register to register Instruction fetch: mabus  PC; – move PC to memory address bus (PCmaEN, ALUmaEN) memory read; – assert memory read signal (mr, RegBmdEN) IR  memory; – load IR from memory data bus (IRld) op  add – send PC into A input, 1 into B input, add (srcA, srcB0, scrB1, op) PC  ALUout – load result of incrementing in ALU into PC (PCld, PCsel) Instruction decode: IR to controller values of A and B read from register file (rs, rt) Instruction execution: op  add – send regA into A input, regB into B input, add (srcA, srcB0, scrB1, op) rd  ALUout – store result of add into destination register (regWrite, wrDataSel, wrRegSel) CS 150 - Fall 2000 - Introduction - 183

Register-Transfer-Level Description (cont’d) How many states are needed to accomplish these transfers? Data dependencies (where do values that are needed come from?) Resource conflicts (ALU, busses, etc.) In our case, it takes three cycles One for each step All operation within a cycle occur between rising edges of the clock How do we set all of the control signals to be output by the state machine? Depends on the type of machine (Mealy, Moore, synchronous Mealy) CS 150 - Fall 2000 - Introduction - 184

CS 150 - Fall 2000 - Introduction - 185 Review of FSM Timing fetch decode execute step 1 step 2 step 3 IR  mem[PC]; PC  PC + 1; rd  A + B A  rs B  rt to configure the data-path to do this here, when do we set the control signals? CS 150 - Fall 2000 - Introduction - 185

FSM Controller for CPU (skeletal Moore FSM) First pass at deriving the state diagram (Moore machine) These will be further refined into sub-states reset instruction fetch instruction decode SW ADD J instruction execution LW CS 150 - Fall 2000 - Introduction - 186

FSM Controller for CPU (reset and inst. fetch) Assume Moore machine Outputs associated with states rather than arcs Reset state and instruction fetch sequence On reset (go to Fetch state) Start fetching instructions PC will set itself to zero mabus  PC; memory read; IR  memory data bus; PC  PC + 1; reset instruction fetch Fetch CS 150 - Fall 2000 - Introduction - 187

FSM Controller for CPU (decode) Operation Decode State Next state branch based on operation code in instruction Read two operands out of register file What if the instruction doesn’t have two operands? instruction decode Decode branch based on value of Inst[15:13] and Inst[3:0] add CS 150 - Fall 2000 - Introduction - 188

FSM Controller for CPU (Instruction Execution) For add instruction Configure ALU and store result in register rd  A + B Other instructions may require multiple cycles instruction execution add CS 150 - Fall 2000 - Introduction - 189

FSM Controller for CPU (Add Instruction) Putting it all together and closing the loop the famous instruction fetch decode execute cycle reset instruction fetch Fetch instruction decode Decode add instruction execution add CS 150 - Fall 2000 - Introduction - 190

CS 150 - Fall 2000 - Introduction - 191 FSM Controller for CPU Now we need to repeat this for all the instructions of our processor Fetch and decode states stay the same Different execution states for each instruction Some may require multiple states if available register transfer paths require sequencing of steps CS 150 - Fall 2000 - Introduction - 191