A Step-By-Step Description of the System Generator Flow Section A A Step-By-Step Description of the System Generator Flow For a Colour Space Convertor In this section, a colour image stored as a bit map file is converted into 3 files containing pixel data for each of the primaries Red, Green and Blue. A script executed in the Matlab domain is used to create these files in the Matlab Workspace These separate files can then be accessed by a Simulink block diagram, which describes the structure of the RGB2YPBPR convertor of Figure 25. The Simulink model contains both an RGB2YPBPR and YPBPR2RGB convertor core, so in addition to being able to review the monochrome YPBPR outputs, we can also review the output of the YPBPR2RGB convertor core as a reconstructed bitmap. This exercise also identifies the need to have prior knowledge of the latency of the cores being used in the Simulink domain; this is easily obtainable from CORE Generator, but it demonstrates that you cannot be totally ignorant of the hardware implementation. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

System Generator Flow - Source Image 362 lines 500 rows 500 pixels/row x 362 rows = 181000 pixels = 4.344 Million bits (24-bit colour). Each pixel = 8-bit Red + 8-bit Green + 8-bit Blue Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

SysGen Flow - Start New Project 1 Start Matlab, and then Simulink Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

SysGen Flow - Open Simulink Project Red, Green and Blue pixel data are loaded from variables in the Matlab Workspace Use a Z-1 token to imply a register. A single register next to the inputs and outputs of the Xilinx domain will get mapped to the IOBs of the device. This will reduce the clock to setup and clock to out times of the FPGA. (i.e., data bandwidth increases.) Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

SysGen Flow - RGB2YPBPR core Note the use of CORE Generator Full multipliers with a constant input! This is None Optimal use of the device, as one input of the mutiplier is constant. A Constant Coefficient Multiplier should be used; however, at present, the CORE Generator Constant Coefficient Multiplier is not supported by the System Generator. It was decided to use the full multipliers to demonstrate the Smart-IP design advantages. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

SysGen Flow - Setup Workspace This Matlab script is used to set up variables in the Matlab workspace. This script scans each pixel of the picture, splitting it into three separate arrays of Red, Green and Blue data. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

SysGen Flow - Set up Workspace Execute the PreProc_flowers.m script to set up Matlab workspace. Notice how the variables appear in the Workspace viewer. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

SysGen Flow - Run the Simulation Having set up the source and destination variables in the Matlab workspace, the simulation can be started. Be prepared to wait a while as it works its way through a lot of data!……. And consider that this is just a single frame. Any temporal processing that requires multiple frames may require considerable time to process. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Run a Post-Processing Script Now run a second script to perform two tasks: 1) Create images of the separate Y Cb Cr outputs; 2) Read the RGB outputs from the YPbPr2RGB convertor and see if the picture that has been converted from RGB to YPbPr and back to RGB has any visible differences from the original. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

SysGen Flow - View the Output Execute the PostProc_flowers.m script to display the Luma and Colour difference channels as images; also, display the reconstructed images. (All RGB2YPBPR channels viewed as monochrome signals.) PB PR Y Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

SysGen Flow - Check the Results Picture In Picture Out, … Oh dear! Something has clearly gone wrong, either in one or both of the conversions; the colours are clearly skewed within this image. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

- Remember to balance latency! Note how the delays are not balanced because we forgot to add delay to this mutliplier. Z-5 Beware! At present, you must add the correct silicon latency to the cores via their masks, because this information isn’t characterized into the current Simulink models. Z-2 Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

SysGen Flow - Corrected output Picture In Picture Out - this is better! The pipeline delays are now balanced, and the image is reconstructed correctly, as the Y, PB and PR components are all associated with the same pixel. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

SysGen Flow - Export VHDL Files Double-click on this icon to set up the System Generator options... Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

SysGen Flow - SysGen Token GUI Select your target technology: - Virtex - Virtex-II - Spartan-II Select a target directory for all the System Generator: -EDIFs -VHDs -TestBenches -Data files Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

SysGen Flow - Generating The Files Generate the output files Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

SysGen Flow - Successful Process Completed. All output files are now written in the target directory and the next stage of the flow can take place...synthesis! Andy Miller © Copyright 2000 Xilinx - All Rights Reserved (Press your “Page Down” key to end the presentation.)