CSE378 Midterm Review Moore’s Law -- What are the two versions?

Slides:

Advertisements

Similar presentations

Pipeline Exceptions & ControlCSCE430/830 Pipelining in MIPS MIPS architecture was designed to be pipelined –Simple instruction format (makes IF, ID easy)

Advertisements

Pipeline Example: cycle 1 lw R10,9(R1) sub R11,R2, R3 and R12,R4, R5 or R13,R6, R7.

The Processor: Datapath & Control

331 W9.1Spring :332:331 Computer Architecture and Assembly Language Spring 2006 Week 9 Building a Single-Cycle Datapath [Adapted from Dave Patterson’s.

Levels in Processor Design

CMPUT Computer Organization and Architecture II1 CMPUT229 - Fall 2003 TopicE: Building a Data Path and a Control Path for a Microprocessor José Nelson.

331 Lec 14.1Fall 2002 Review: Abstract Implementation View  Split memory (Harvard) model - single cycle operation  Simplified to contain only the instructions:

Preparation for Midterm Binary Data Storage (integer, char, float pt) and Operations, Logic, Flip Flops, Switch Debouncing, Timing, Synchronous / Asynchronous.

Computer Structure - Datapath and Control Goal: Design a Datapath  We will design the datapath of a processor that includes a subset of the MIPS instruction.

CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 TopicH: Building a Data Path and a Control Path for a Microprocessor José Nelson.

CS 61C discussion 11 (1) Jaein Jeong 2002 Draw the data path: ADD or SUB Clk 555 RwRaRb bit Registers Extender Clk WrEn Adr Data Memory ALU Instruction.

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures1 Machine instructions execution steps (1) FETCH = Read the instruction.

The Datapath Andreas Klappenecker CPSC321 Computer Architecture.

The Multicycle Processor CPSC 321 Andreas Klappenecker.

Dr. Iyad F. Jafar Basic MIPS Architecture: Multi-Cycle Datapath and Control.

Supplementary notes for pipelining LW ____,____ SUB ____,____,____ BEQ ____,____,____ ; assume that, condition for branch is not satisfied OR ____,____,____.

COSC 3430 L08 Basic MIPS Architecture.1 COSC 3430 Computer Architecture Lecture 08 Processors Single cycle Datapath PH 3: Sections

Computer Architecture and Design – ECEN 350 Part 6 [Some slides adapted from A. Sprintson, M. Irwin, D. Paterson and others]

1 A single-cycle MIPS processor  An instruction set architecture is an interface that defines the hardware operations which are available to software.

CSE331 W10.1Irwin&Li Fall 2006 PSU CSE 331 Computer Organization and Design Fall 2006 Week 10 Section 1: Mary Jane Irwin (

PC Instruction Memory Address Instr. [31-0] 4 Fig 4.6 p 309 Instruction Fetch.

Datapath and Control AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data.

1 CS/COE0447 Computer Organization & Assembly Language Chapter 5 Part 2.

MIPS processor continued

Datapath and Control AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data.

Chapter 4 From: Dr. Iyad F. Jafar Basic MIPS Architecture: Multi-Cycle Datapath and Control.

Computer Architecture Lecture 6.  Our implementation of the MIPS is simplified memory-reference instructions: lw, sw arithmetic-logical instructions:

ECE/CS 552: Single Cycle Control Path

Single-cycle CPU Control

Access the Instruction from Memory

EE204 Computer Architecture

MIPS Microarchitecture Single-Cycle Processor Control

Single Cycle CPU - Control

Multi-Cycle Datapath and Control

CS161 – Design and Architecture of Computer Systems

Chapter 5: A Multi-Cycle CPU.

CS 230: Computer Organization and Assembly Language

Computer Architecture

IT 251 Computer Organization and Architecture

Instruction Format MIPS Instruction Set.

Single Cycle Processor

Multi-Cycle CPU.

CS/COE0447 Computer Organization & Assembly Language

Discussion Session Week 10

MIPS processor continued

CS/COE0447 Computer Organization & Assembly Language

Single-Cycle CPU DataPath.

CS/COE0447 Computer Organization & Assembly Language

CSCI206 - Computer Organization & Programming

CS/COE0447 Computer Organization & Assembly Language

CS/COE0447 Computer Organization & Assembly Language

Datapath & Control MIPS

Levels in Processor Design

Composing the Elements

Composing the Elements

Systems Architecture I

The Processor Lecture 3.2: Building a Datapath with Control

COSC 2021: Computer Organization Instructor: Dr. Amir Asif

Control Unit (single cycle implementation)

Instruction Format MIPS Instruction Set.

5.5 A Multicycle Implementation

Data Path Diagrams.

MIPS processor continued

CS/COE0447 Computer Organization & Assembly Language

Systems Architecture I

FloorPlan for Multicycle MIPS

Control Unit (single cycle implementation)

The Processor: Datapath & Control.

Processor: Datapath and Control

CS/COE0447 Computer Organization & Assembly Language

Presentation transcript:

CSE378 Midterm Review Moore’s Law -- What are the two versions? Is Moore’s Law a law? Explain what an instruction set architecture is [ISA] What do the terms RISC and CISC mean? 12/9/2018 CSE378 Review

MIPS ISA Give the uses of the fields of an R-type instruction: [31-26], [25-21], [20-16], [15-11], [10-6], [5-0] Give the numbers of two registers whose use is specified in the ISA Give the numbers of two registers whose use is agreed-on by programming language convention Give the numbers of two registers whose use is agreed-on by programming convention Explain big-endian and little-endian memory layout 12/9/2018 CSE378 Review

More MIPS Explain the difference between instructions performing “signed” and “unsigned” arithmetic Explain the operation of the MIPS memory operations: Load and Store What is a “pseudo-op” or “pseudo instruction”? How is it that the add and subtract instructions can have the same opcode? Explain how to load a full word constant into register $4 12/9/2018 CSE378 Review

ALU Bit-slice Give the control signals for NOR What value does “Less” get assigned? Write a poem about the beauty of 2s- complement math 12/9/2018 CSE378 Review

Load Word Give the control line settings for LW 12/9/2018 CSE378 Review

Decoding SW Explain what changes if SW’s opcode were 110000, and the “don’t cares” were to be 1 Signal R-type lw sw beq Op5 0 1 1 0 Op4 0 0 0 0 Op3 0 0 1 0 Op2 0 0 0 1 Op1 0 1 1 0 Op0 0 1 1 0 RegDest 1 0 X X ALUSrc 0 1 1 0 MemtoReg 0 1 X X RegWrite 1 1 0 0 MemRead 0 1 0 0 MemWrite 0 0 1 0 Branch 0 0 0 1 ALUOp1 1 0 0 0 ALUOp0 0 0 0 1 OR AND Op5 Op4 Op3 Op2 Op1 Op0 RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOp0 12/9/2018 CSE378 Review

Multicycle MIPS Explain purpose of MDR Give control for 2nd cycle 12/9/2018 CSE378 Review