ECE 465 Lecture Notes # 1 Introduction to Digital Design Shantanu Dutt ECE Dept. UIC

—the analog BW is proportional to n, the the # of distinct values or levels, while the corresponding digital BW is proportional to log n (or more exactly to Vdd(log n))

i.e., 2’s complement number system, floating-point number system, etc.

Derived from direct logic inputs or encoded from sensor inputs  Pure if-then-else type constructs can be implemented using combinational circuits  Loops need to be implemented using sequential circuits, since the circuit/system needs to at least “remember” whether currently “in the loop or out of it” in order to perform the function(s) in the loop or some other function(s). There are also other function types besides loops that a seq. circuit performs. Direct logic outputs or decoded to provide actuator inputs Derived from logic inputs (direct or encoded) and from current loop state.

A purely combinational circuit  Pure if-then-else type constructs can be implemented using combinational circuits  Loops need to be implemented using sequential circuits, since the circuit/system needs to at least “remember” what it needs to re-do in each iteration of the loop in order to perform the combinational function(s) in the loop. There are also other function types besides loops that a seq. circuit performs. if-then-else or unconditional code for f (e.g., a = b*c) if-then-else code or unconditional code for g (e.g., x = a + d) a b, c x f (comb.) g (comb.) d A purely combinational circuit

A sequential circuit/system Using a seq. circuit to control loop/iterative processing by combinational ckts (also called functional units): repeat do f ; (if-then-else or uncond. code like a = a + b) until cond C0 (e.g., a > 100) do g; (if-then-else or uncond. code for g like x = a + d) In the above loop the concept of “enabling” combinational function(s) within the loop arises. E.g., f is enabled, i.e., its output is enabled to go to the next function g, only after the loop has finished, i.e., when C0 is true AFTER this, f’s operation and enabling has to stop AFTER this, the system needs to activate a completion signal for the external world when g finishes. In general, the system needs to remember which stage of data processing it is in to process the data of that stage, and hence a sequential circuit is needed to control the system—do the right data processing at the right time. a f (comb /seq) g (comb.) register C0 = 1 C0 = 0 ld_reg = 1 cntinp = 4 ld_cnt = 1 ld_reg wait state (until g done) reset Seq. circuit to implement the repeat loop + a bit more. C0 cnt != 0 Counter cntinp ld_cnt cnt = 0 cntdn cntdn=1 cnt compl =1 1 Ghz clock 4 delay = 5 cc’s a,b Loading 4 (n) in the counter, and then counting down in order to wait for 5 (n+1) ccs for g to finish. A sequential circuit/system Note: Besides implementing loops, there are other situations in which a circuit will need to remember information from the past, and if so, it has to be a sequential circuit.

. This represents a complete set of logic operations. Is this set minimal (taking out any operations renders it incomplete)? Are there other such sets?

Binary System:

Role of Logic for Implementation of Binary Functions Input and output binary encoding (can represent numbers/colors/on-off signals/etc.) based purely on required functionality; nothing to do with logic yet x1 x2 x3 f 1 TT with input & output encoding for some required functionality Logic plays a central role in digital circuit design as follows. Can “see” input digital signals 1 (high voltage) and 0 (low voltage) as T and F, and determine digital outputs (1/0 = T/F) based on functionality required . Then each o/p can be seen as a logic function of inputs that can be composed with AND/OR/NOT operators (e.g., f = x1 AND x2 OR x2 AND NOT(x3) for above TT). Further, if we have electronic components that implement AND/OR/NOT, we can get a circuit to implement the function producing o/p f!

There are two switches S1 and S2 to control a light bulb (e. g There are two switches S1 and S2 to control a light bulb (e.g., one switch near each door of a room w/ 2 doors). Design a logic circuit so that the bulb can be controlled (essentially, toggled) by either switch (i.e., by flicking/pushing either switch). Assume an initial condition S1 S2 Z np/0 Off/0 p/1 On/1 S1 S2 Z np/0 On/1 p/1 Off/0 1-switch flick transition arrows (verifying consistency of corresponding o/p transitions) Legend: np: not pushed (or, say, “up” posn) p: pushed (or, say, “down” posn) Design Steps (for small-size designs w/ up to around 6 vars; we will later learn about hierarchical or divide-and-conquer strategies for larger designs) 1a. If TT can be obtained directly (due to the nature of the problem statement), then get a “symbolic” TT, encode inputs and outputs, get the logic/Boolean (0/1) TT, and go straight to the minimization step (Step 4). Otherwise go to Step 1b.

Alternate Statement Design Steps (for small-size designs w/ up to around 6 vars; we will later learn about hierarchical or divide-and-conquer strategies for larger designs) 1b. (symbolic)

(Canonical SOP)

FPGAs—will do later)

AB

Drain Source

nMOS Transistor – Logic ‘1’ Transfer VT,MP (or Vth) is the threshold voltage of the nMOS transistor. The gate-source voltage Vgs needs to be >= Vth for an nMOS transistor to conduct Ack: From http://www.cse.fau.edu/~ankur/courses/IntroVLSIDesign/Pass%20Transistor%20Logic.ppt

nMOS Transistor – Logic ‘0’ Transfer Thus, an nMOS transistor conducts a weak 1 and a strong 0 For a pMOS transistor to conduct, the gate-source voltage Vgs <= -Vth, and an analogous analysis shows that with the transistor conducting (Vg = 0): (a) the lowest output voltage can be Vth (any lower and the trans. switches off), and (b) the highest voltage can be Vdd. Thus, a pMOS transistor conducts a weak 0 and a strong 1 Ack: From http://www.cse.fau.edu/~ankur/courses/IntroVLSIDesign/Pass%20Transistor%20Logic.ppt

GATES IN SERIES The output can thus be a very weak 1 VA=Vdd ≥ Vth Vy; max Vy = VA- Vth = Vdd - Vth VB=Vdd Vx; max Vx = VB- Vth = Vdd - Vth ≥ Vth Vdd Vdd -Vt Vdd -2Vt Vdd -3Vt Vdd -4Vt weak 1 very weak 1 The output can thus be a very weak 1 Ack: From http://www.cse.fau.edu/~ankur/courses/IntroVLSIDesign/Pass%20Transistor%20Logic.ppt

CMOS TRANSMISSION & LOGIC GATES Thus an nMOS transistor passes a strong 0 and a weak 1. A similar analysis (for pMOS, gate to source voltage has to be < the (negative) threhold voltage VT for transistor to conduct) shows that a pMOS transistor passes a strong 1 and a weak 0. This is the basis of CMOS logic gates, where pMOS transistors are used in the “top” n/w connected to Vdd to conduct a strong or good 1, and nMOS transistors are used in the “bottom” or complementary n/w to conduct a strong 0. Also, can Combine the two to make a CMOS pass gate, called a transmission gate, which will pass a strong 0 and a strong 1. VA=0 VB=0 ≤ -Vth ≤ -Vth Vx; max Vx = Vdd Ack: Partly from http://www.cse.fau.edu/~ankur/courses/IntroVLSIDesign/Pass%20Transistor%20Logic.ppt

Problem w/ Large Switching Networks Even though pMOS conducts a good 1, a long series of pMOS transistors for a many-input gate can lead to excessive resistance R and thus a large output delay RC, where C is the load capacitance driven by the gate. Example: Consider an 8-variable NOR function f = (x7+x6+x5+x4+x3+x2+x1+x0)’. Its implementation using a single n/w is given below; we assume that a pMOS transistor has an on-resistance of Rp. Note that f = x7’x6’ ….. x1’x0’ Vdd=3v x7 x6 x5 x4 x3 x2 x1 x0 f R = 8Rp Output delay = 8RpC Corresponding compl. n/w (f’=x7+x6+….+x1+x0) GND

Problem with Large Switching Networks (contd) The solution for avoiding such excessive delay is using a number of smaller switching n/ws over “parallel” paths [otherwise, if all the smaller n/ws are on one sequential path, there will be no or little delay improvement]. Thus we need to break down a large function (function w/ many variables—generally > 6) into smaller ones that can each be implemented using smaller n/ws. This happens to a large extent when a function is represented as an SOP or POS expression (it is lready broken down into ANDs and ORs) but not always (e.g., an AND or OR term may have a large # of vars). E.g., the 8-i/p NOR function f can be decomposed as (and then impl as below): f = [(x7+x6+x5+x4) + (x3+x2+x1+x0)]’ = [(x7’x6’x5’x4’)’ + (x3’x2’x1’x0’)’]’ = NOR(NAND(x7’,x6’,x5’,x4’), NAND(x3’,x2’,x1’,x0’)). Alternatively, f = (x7+..+ x4)’ (x3+..+x0)’ = AND(NOR(x7,..,x4), NOR(x3,..x0)) = NOT(NAND(NOR(x7,..,x4), NOR(x3,..x0)))

Problem with Large Switching Networks (contd) The 8-i/p NOR function f can be decomposed as (and then impl as below): f = [(x7+x6+x5+x4) + (x3+x2+x1+x0)]’ = [(x7’x6’x5’x4’)’ + (x3’x2’x1’x0’)’]’ = NOR(NAND(x7’,x6’,x5’,x4’), NAND(x3’,x2’,x1’,x0’)). Vdd=3V x7’ Vdd=3V x3’ Rp x2’ x0’ x1’ Compl n/w for h Longest-delay paths (parallel w/ other paths) x6’ x7’ x6’ x5’ x4’ x5’ g g h Vdd f x4’ x3’ h x2’ 2Rp x1’ x0’ delay = 4RpC Rp delay = 2RpC delay = 4RpC Parallel paths GND Compl n/w for g GND Compl n/w for NOR GND Total delay = ? 4Rp 4Rp Rp Note: Delay of a circuit = delay of its longest-delay path from input [i/p] to output [o/p] What about for an n-i/p NOR (n > 8)?

Problem with Large Switching Networks (contd) These small switching networks are called gates Thus need to use small to medium-size (<= 4 inputs) gates to implement large logic functions strong 1 Vdd strong 1 strong 0 X strong 1 A cascade or series of NAND/NOR gates will produce strong 1’s as well as strong 0’s as well as smaller delay than a large switching n/w for the corresponding logic expression.

Circuit Delay—Definition, Model, Computation Assume R is the on-resistance of a single nMOS or pMOS transistor, and C its i/p or gate capacitance. Output capacitive load if driving 1 nand / nor / and /or / not gate i/p = 2C (2 trans. gate i/ps, 1 pmos, 1 nmos, driven) Vdd RC-type output delay = (kR)*(2C) = k*(2RC) = k delay units (1 delay unit = 2RC). Applies to nand / nor / and /or / not gate driving 1 input of a similar gate type k inputs Rg OR 2C GND Max gate resistance Rg (can be in top/bottom n/w in nand / nor / and / or / not gate)  k pmos/nmos trans. in series = kR GND Fig. 1: CMOS realization of a 2-i/p NAND gate Fig. 2: A path of a circuit and its delay g1 g2 g3 g4 Rg(g1)*CL(g2) = 2 units + Rg(g2)*CL(g3) = 3 units + Rg(g3)*CL(g4) + Rg(g4)*CL(op) A circuit path (g1g2g3g4output) Path delay = 9 units See next 2 slides for a detailed derivation of above simple delay model

Circuit Delay—Definition, Model, Computation (cont’d) Assume R is the on-resistance of a single nMOS or pMOS transistor, and C its i/p or gate capacitance. Then the worst-case “top” network resistance Rtop of a gate gi is the k*R, where k = max. # of transistors in series in the top n/w of gi. Similarly, for the resistance Rbot of the “bottom” or complementary n/w of gi. For most gates (NAND,NOR, AND, OR, XOR, XNOR), one or both of Rtop and Rbot = k*R. If CL is the capacitive load seen by a gate gi (generally = the sum of gate capacitances C of the transistors of the gate(s) that gi drives), then the delay in gi driving its output from 0  1 is Rtop* CL and the delay in gi driving its output from 1  0 is Rbot* CL . In general, we define gate res. Rg = max(Rtop , Rbot), and the delay of its output signal as Rg* CL = k*R*CL Example: For the 2 i/p NAND gate in Fig. 1, Rtop = R (note that in the worst-case only 1 pMOS transistor is on, so the res. then is R, and *not* R/2), Rbot = 2R. Thus Rg = 2R, and the gate’s output delay = Rg*CL = 2R*CL . If the gate is driving a 2-input NAND/NOR/AND/OR gate, then = CL= 2C. What is CLof a 2-input XOR or XNOR gate? The delay of a path = S (output delays of gates on the path). The delay of the path shown in Fig. 2 = [d(g1) + Rg(g1)*CL(g2)] + [d(g2) + Rg(g2)*CL(g3)] + [d(g3) + Rg(g3)*CL(g4)] + [d(g4) + Rg(g4)*CL(op)], where CL(op) is the load at the output of the path and d(gi) is the “intrinsic” delay of a gate gi to switch from off to on. Fig. 1: CMOS realization of a 2-i/p NAND gate Fig. 2: A path of a circuit and its delay g1 g2 g3 g4 Rg(g1)*CL(g2) + Rg(g2)*CL(g3) + Rg(g3)*CL(g4) + Rg(g4)*CL(op) A circuit path (g1g2g3g4output) Note: For NAND/NOR/AND/OR/NOT gates: Driving resistance R is proportional to # of gate inputs of driving or source gate g1, load capacitance of input of driven or sink gate g2 it drives is always 2C irrespective of the # of g2’s inputs, and thus g1  g2 delay (ignoring intrinsic gate delay) is prop.to g1’s # of inputs

Circuit Delay (cont’d) The delay of a path = S (output delays of gates on the path). The delay of the path shown in Fig. 2 = [d(g1) + Rg(g1)*CL(g2)] + [d(g2) + Rg(g2)*CL(g3)] + [d(g3) + Rg(g3)*CL(g4)] + [d(g4) + Rg(g4)*CL(op)], where CL(op) is the load at the output of the path and d(gi) is the “intrinsic” delay of a gate gi to switch from off to on. Thus, assumimg that the d(gi) for all 2-i/p gates is the same and = d(g), the path delay = 4*d(g) + 2R*2C + 2R*2C + 2R*2C + 2R* CL(op) = 4*d(g) + 12RC + 2R* CL(op) = 4*d(g) + 16RC if CL(op) = 2C. If we ignore the d(gi)’s (which are typically small compared to the RC delays), the rest of the delay is the RC delay, which for this ex. = 16RC = 4*(2R*2C) The 2C part of the delay expression will remain unchanged (for nand/nor/and/or gates) irrespective if the gate sizes # of i/ps). However the 2R part in each term will change to kR where k = # of i/ps (for nand/nor/and/or gates) If the gates in Fig. 2 were all 3-i/p gates, the RC delay expression will be 4*(3R*2C) = 24RC = (3/2)*(16RC) (as the # of i/ps change from 2 to 3, delay increases proportionately by a factor of 3/2). Thus the delay is proportional to the sum of the # of each inputs along a path (8 for the path w/ 2-i/p gates and 12 if the gates are 3 i/ps) as long as each gate is driving only one other gate input. Thus a simple delay model we will use is that the delay of a gate w/ k i/ps = k, and add up this simplified gate-i/p delay units along a path to get the path’s delay. In the ex. below is will be 2+2+2+2 = 8 gate-i/p units Finally, the delay of a circuit is the delay in the longest (max-delay) path of the circuit from primary inputs to any output Fig. 1: CMOS realization of a 2-i/p NAND gate Fig. 2: A path of a circuit and its delay g1 g2 g3 g4 Rg(g1)*CL(g2) + Rg(g2)*CL(g3) + Rg(g3)*CL(g4) + Rg(g4)*CL(op) A circuit path (g1g2g3g4output)

Determining Circuit Delay (intrinsic gate delay) + RC delay at gi’s o/p Start from 1st level gates and go forward to 2nd level, etc. until the output gate is reached. Boundary condition: Primary i/ps are available at time 0. Assume that the intrinsic delay d(gi) of each gate except xor/xnor = 1.5 ns, that of xor/xnor gates is 3.5 ns, and each RC delay between a driving gate and driven i/p is 2.5 ns. Thus i/p -> o/p delay for each gate except xor/xnor = 4 ns, while that for xor/xnor is 6 ns