COSC 2021: Computer Organization Instructor: Dr. Amir Asif Department of Computer Science York University Handout # 7: Arithmetic Logic Unit (ALU) Topics: 1. Boolean Algebra 2. Designing an ALU Patterson: Appendix B.1 – B.7 provided in the CD

Logical Operations: AND, OR, NOT, Multiplexer AND Gate: OR Gate Notation a b c Symbol Truth Table 1 c = a · b Truth Table 1 c = a + b b a a b c Notation Symbol

Logical Operations: AND, OR, NOT, Multiplexer NOT Gate (Inverter): Multiplexer Notation Symbol Truth Table c b 1 a Notation Symbol Truth Table b 1 a c d

Boolean Algebra (1) Logic Operations can be expressed in terms of logic equations For the above figure, the output To implement the above digital circuit, 2 AND, 1 NOT and 1 OR gates are required Can we simplify the above circuit? A B C

Boolean Algebra (1) Expressions A + 0 = A Identity Law A · 1 = A Zero and One Law A + 1 = 1 A · 0 = 0 Inverse Law A + Ā = 1 Ā · 0 = 0 Commutative law A + B = B + A A · B = B · A Associative Law A + (B + C)= (A + B) + C A · (B · C) = (A · B) · C Distributive Law A · (B + C) = (A · B) + (A · C) A + (B · C) = (A + B) · (A + C) DeMorgan Law (A + B) = A · B (A · B ) = A + B

Boolean Algebra (2) Activity 1: Simplify the expressions: Activity 2: Implement simplified expressions for (a) – (e) using OR, AND, and NOT gates

Combinational Logic: Design of a 1-bit adder (1) Example: Design an 1-bit adder with Carry-in Step 1: Construct the truth table for an 1-bit adder 3 binary inputs imply (23 = 8) entries in the truth table INPUTS OUTPUTS a b c (CarryIn) CarryOut Sum 1 S u m C a r y I n O t b Truth Table for 1-bit adder Schematic of a 1-bit adder

Combinational Logic: Design of a 1-bit adder (2) Step 2: Derive the Boolean expression for each output from the truth table INPUTS OUTPUTS a b c (CarryIn) CarryOut Sum 1

Combinational Logic: Design of a 1-bit adder (3) Step 3: Simplify the Boolean expression Step 4: Implement the simplified Boolean expression using OR, AND, and NOT gates Activity: Implement the hardware for the Sum ouput of the 1-bit adder b C a r y O u t I n

1-bit adder Recall the digital circuit of a 1-bit adder We will enhance the 1-bit adder to develop a prototype ALU for MIPS S u m C a r y I n O t b Schematic of a 1-bit adder b C a r y O u t I n Digital Circuit of a 1-bit adder (CarryOut only)

1-bit ALU with AND, OR, and Addition The 1-bit adder is supplemented with AND and OR gates A multiplexer controls which gate is connected to the output b 2 R e s u l t O p r a i o n 1 C y I ALU Control Lines Result Carry In Operation 0 = (00)two AND 1 = (01)two OR 2 = (10)two add a x b R e s u l t C r y I n O p i o A L U 1-bit ALU with AND, OR, and Addition capability Schematic

32-bit ALU w/ AND, OR, and ADD e s u l t 3 1 a b C r y I n 2 O p i o A L U The 1-bit ALU can be cascaded together to form a 32 bit ALU Which operation is performed is controlled by the Operation bus The designed 32-bit ALU is still missing the subtraction, slt (set if less than), and conditional branch operations ALU Control Lines Result Carry In Operation 0 = (00)two AND 1 = (01)two OR 2 = (10)two add

1-bit ALU with AND, OR, Addition, and Subtraction Recall that subtraction is performed using 2’s complement arithmetic We calculate the 2’s compliment of the sub-operand and add to the first operand 2 R e s u l t O p r a i o n 1 C y I B v b ALU Control Lines Result Binvert Carry In Operation 0 = (00)two AND 1 = (01)two OR 2 = (10)two add 1 sub 1-bit ALU with AND, OR, Addition, and Subtraction capability

1-bit ALU with AND, OR, Add, Sub, and SLT (1) Since we need to perform one more operation, we increase the number of inputs at the multiplexer by 1 and label the new input as Less SLT operation: if (a < b), set Less to 1 => if (a – b) < 0, set Less to 1 SLT operation can therefore be expressed in terms of a subtraction between the two operands. If the result of subtraction is negative, set Less to 1. How do we determine if the result is negative? 3 R e s u l t O p r a i o n 1 C y I B v b 2 L 1-bit ALU with AND, OR, Add, Sub, and SLT capability

1-bit ALU with AND, OR, Add, Sub, and SLT (2) Use the sign bit obtained from the 1-bit ALU at the MSB position to indicate the result of SLT. B i n v e r t O p e r a t i o n C a r r y I n a 1 R e s u l t b 2 1 L e s s 3 Set C a r r y O u t 1-bit ALU of MSB (bit 31) with AND, OR, Add, Sub, and SLT capability

1-bit ALU with AND, OR, Add, Sub, and SLT (3) In fact we also include the overflow circuit within the 1-bit ALU at the MSB 1-bit ALU of MSB (bit 31) with AND, OR, Add, Sub, SLT, and overflow 3 R e s u l t O p r a i o n 1 C y I B v b 2 L S f w d c

1-bit ALU (4) ALU ALU 3 1 b 2 L f w d c 3 1 2 3 R e s u l t O p r a i o n 1 C y I B v b 2 L S f w d c 3 R e s u O p r a t i o n 1 C y I B v b 2 L l 1-bit ALU for MSB (bit 31) 1-bit ALU for bits (0 – 30) ALU ax bx Less Result Binvert Carry In Carry Out Operation Carry In Binvert Operation ax ALU Set bx Result Less Overflow Carry Out

32-bit ALU w/ And, OR, Add, Subtract, and SLT e t a 3 1 R s u l 2 b O v r f o w C y I n A L U p i B The 1-bit ALU’s can be cascaded together to form a 32 bit ALU Operations are controlled by the Operation bus Note that Binvert is always the same as Carry In To test equality between a and b, subtract a and b and check if the result is 0. ALU Control Lines Result Binvert Carry In Operation 0 = (00)two AND (a·b) 1 = (01)two OR (a+b) 2 = (10)two Add sum(a,b) 1 2 = (11)two Subtract (a - b) 3 = (11)two SLT Set Result0 if (a < b)

32-bit ALU w/ And, OR, Add, Subtract, SLT, and Equality Test 1 R s u l 2 O p r i o n b v f w B g Z A L U C y I ALU Control Lines Result Binvert Carry In Operation 0 = (00)two AND (a·b) 1 = (01)two OR (a+b) 2 = (10)two Add sum(a,b) 1 Subtract (a - b) 3 = (11)two SLT if (a < b) Result0 = 1 Test Equality Zero = 1 if (a < b)

32-bit ALU w/ And, OR, Add, Subtract, SLT, and Equality Test 1 R s u l 2 O p r i o n b v f w B g Z A L U C y I A L U R e s u l t Z r o O v f w a b p i n C y