Timer Source: http://www.edsim51.com/8051Notes/8051/timers.html under http://www.edsim51.com/8051Notes/index.html

The basic 8051 has two 16-bit on-chip timers: (1) Timer 0 (TH0TL0) & (2) Timer 1 (TH1TL1) They can be used for (1) timing durations, or (2) counting external events.

Timer Mode Register (TMOD) TMOD (Timer Mode Register ) Bit Name Timer Description 7 Gate 1 Gate bit; when set, timer only runs while INT-bar is high. This bit is used in conjunction with interrupts and will be dealt with later. 6 C/T-bar Counter/timer select bit; when set timer is an event counter, when cleared timer is an interval timer. 5 M1 Mode bit 1 4 M0 Mode bit 0 3 Gate bit; when set, timer only runs while INT-bar is high. 2

Timer Modes M1 M0 Mode Description 13-bit timer mode (this mode exists simply to keep the 8051 backwards compatible with its predecessor, the 8048, which had a 13-bit timer) - we will not be using mode 0. 1 16-bit timer mode 2 8-bit auto-reload mode 3 Split timer mode - this mode will be dealt with at a later stage X = 1 for Timer 1 X = 0 for Timer 0

Note on the 8-bit auto-reload mode Example 6 of edsim51 MOV TMOD, #2H ; set timer 0 as 8-bit auto-reload interval timer MOV TH0, #-50 ; | put -50 into timer 0 high-byte - this reload value, ; | with system clock of 12 MHz, will result in a timer 0 overflow every 50 us MOV TL0, #-50 ; | put the same value in the low byte to ensure the timer starts counting from ; | 236 (256 - 50) rather than 0 TL0 (binary) Signed value Unsigned value  00000010 2 00000001 1 00000000 Counting ends 11111111 -1 255 11111110 -2 254 11001100 -48 108 11001101 -49 107 Counting starts 11001110 -50 106

Timer Control Register TCON (Timer Control Register) Bit Symbol Bit Address Description 7 TF1 8FH Timer 1 overflow flag; set by hardware upon overflow, cleared by software. 6 TR1 8EH Timer 1 run-control bit; manipulated by software - setting starts timer 1, resetting stops timer 1. 5 TF0 8DH Timer 0 overflow flag; set by hardware upon overflow, cleared by software. 4 TR0 8CH Timer 0 run-control bit; manipulated by software - setting starts timer 0, resetting stops timer 0. 3 IE1 8BH The bottom four bits of TCON are used in conjunction with interrupts. ITx controls the triggering condition of external x interrupt. = 1: negative-edge triggering = 0: low-level triggering IEx is the interrupt flag for external interrupt x , where x = 0 or 1 2 IT1 8AH 1 IE0 89H IT0 88H SETB TR0; start timer 0 SETB TR1; start timer 1 CLR TR0; stop timer 0 CLR TR1; stop timer 1

Clock Source When the timer is operating as an interval timer it is being clocked by the internal clock. This internal clock, usually 12MHz, is actually divided by twelve to yield a reasonable clock frequency for most applications - therefore, the internal clocking signal is usually 1MHz). When the timer is operating as an event counter it is triggered by an external source connected to pin T0 (port 3, pin 4) for timer 0 and pin T1 (port 3, pin 5) for timer 1.