Advanced FPGA Based System Design Lecture-1 Introduction to the Subject By: Dr Imtiaz Hussain imtiaz.hussain@faculty.muet.edu.pk

Outline Boolean Logic Boolean Variables and Expressions Boolean Algebra Logic Gates Mathematical Operations Logic Implementation General Purpose ICs Special Purpose ICs PLDs

Boolean Logic (Basis of Digital Electronics) Computer CD & DVD players IPod Cell phone HDTV Digital cameras

Digital Electronics Sound is an analog signal. On a CD, digital sound is encoded as 44.1 kHz, 16 bit audio. The original wave is 'sliced' 44,100 times a second - and an average amplitude level is applied to each sample. 16 bit means that a total of 65,536 different values can be assigned, or quantized to each sample. DVD-Audio can be 96 or 192 kHz and up to 24 bits resolution

George Boole George Boole, a British mathematician (1815-1864). Logic and math are equivalent. All math functions can be determined using these 3 primary Boolean logic operators: AND, OR, and NOT.

Logic operators fruit AND vegetables AND cereal AND narrows your search, OR broadens your search, and NOT is used to exclude concepts. fruit AND vegetables AND cereal fruit OR vegetables OR cereal fruit NOT apples Fruit Vegetables cereals

Boolean Algebra Boolean algebra provides the operations and the rules for working with the set {0, 1}. These are the rules that underlie electronic circuits, and the methods we will discuss are fundamental to FPGA design. We are going to focus on three operations: Boolean complementation, Boolean sum, and Boolean product

Boolean Operations The complement is denoted by a bar. It is defined by The Boolean sum, denoted by + or by OR, has the following values: 1 + 1 = 1, 1 + 0 = 1, 0 + 1 = 1, 0 + 0 = 0 The Boolean product, denoted by  or by AND, has the following values: 1  1 = 1, 1  0 = 0, 0  1 = 0, 0  0 = 0

Boolean Functions and Expressions Definition: Let B = {0, 1}. The variable x is called a Boolean variable if it assumes values only from B. Boolean functions can be represented using expressions made up from the variables and Boolean operations.

Boolean Functions and Expressions Example: Give a Boolean expression for the Boolean function F(x, y) as defined by the following table: x y F(x, y) 1 solution: F(x, y) = x.y

Boolean Functions and Expressions Give a Boolean expression for the Boolean function F(x, y) as defined by the following table: x y F(x, y) 1

Boolean Functions and Expressions Another Example: 1 F(x, y, z) z y x Possible solution II: F(x, y, z) = (-(xz))(-y) Possible solution III: F(x, y, z) = -(xz + y) Fall 2002 CMSC 203 - Discrete Structures

Definition of a Boolean Algebra Definition: A Boolean algebra is a set B with two binary operations + and ., elements 0 and 1, and a unary operation – such that the following properties hold for all x, y, and z in B: x + 0 = x and x . 1 = x (identity laws) x + x’ = 1 and x . x’ = 0 (domination laws) (x + y) + z = x + (y + z) and (x . y) . z = x . (y . z) and (associative laws) x + y = y + x and x . y = y . x (commutative laws) x + (y . z) = (x + y) . (x + z) and x . (y + z) = (x . y) + (x . z) (distributive laws)

Order of precedence of Boolean operators The order of operations is: AND, NOT, OR, XOR Parentheses are used to override priority. Expressions in parentheses are processed first. Parentheses are used to organize the sequence and groups of concepts.

Basis for digital computers The true-false nature of Boolean logic makes it compatible with binary logic used in digital computers. Electronic circuits can produce Boolean logic operations. Circuits are called gates. NOT AND OR

CMSC 203 - Discrete Structures Logic Gates There are three basic types of gates: Inverter (NOT gate) x y x+y OR gate x y xy AND gate Fall 2002 CMSC 203 - Discrete Structures

Logic Gates Example: How can we build a circuit that computes the function ? xy + (-x)y x y xy -x (-x)y

Write out logic statements using Boolean operators for these. You have a buzzer in your car that sounds when your keys are in the ignition and the door is open. You have a fire alarm installed in your house. This alarm will sound if it senses heat or smoke. There is an election coming up. People are allowed to vote if they are a citizen and they are 18. To complete an assignment the students must do a presentation or write an essay.

How do we use gates to add two binary numbers? Binary numbers are either 1 or 0. Have two outputs. Need a gate to produce each output. 1 + 0 + 1 00 01 10 A B Q CO 1

How do I add larger numbers? You can write any number in binary.

Add binary numbers. Adding larger number just adds more columns.

Binary Subtraction Work the columns right to left subtracting in each column. If you must subtract a one from a zero, you need to “borrow” from the left, just as in decimal subtraction. Subtract 11 from 9 7 from 10

Binary Multiplication As an example of binary multiplication we have 101 times 11,    101   x11 First we multiply 101 by 1, which produces 101. Then we put a 0 as a placeholder as we would in decimal multiplication, and multiply 101 by 1, which produces 101.   101   x11   101  1010  <-- the 0 here is the placeholder The next step, as with decimal multiplication, is to add. The results from our previous step indicates that we must add 101 and 1010, the sum of which is 1111.   101   x11   101  1010 1111

Binary Division 11 11 )1011 -11 101 -11 10 <-- remainder, R Binary  is almost as easy, and involves our knowledge of binary multiplication. Take for example the division of 1011 into 11.          11    11 )1011        -11          101           -11            10  <-- remainder, R

Logic Implementation General Purpose Integrated Circuits Special Purpose ICs Programmable Logic Devices (PLDs)

Logic Implementation General Purpose Integrated Circuits

Logic Implementation 1-bit Adder using general purpose ICs A B Q CO 1

Logic Implementation 8-Bit adder using General purpose ICs

Logic Implementation 8-bit adder require 16 XOR gates 29 AND gates 16 NOT gates

Logic Implementation Special purpose ICs are used to solve this problem

204424 Digital Design Automation Why Make ICs Integration improves size speed power Integration reduce manufacturing costs (almost) no manual assembly December 26, 2018 204424 Digital Design Automation

204424 Digital Design Automation IC Evolution SSI – Small Scale Integration (early 1970s) contained 1 – 10 logic gates MSI – Medium Scale Integration logic functions, counters LSI – Large Scale Integration first microprocessors on the chip VLSI – Very Large Scale Integration now offers 64-bit microprocessors, complete with cache memory (L1 and often L2), floating-point arithmetic unit(s), etc. December 26, 2018 204424 Digital Design Automation

Moore’s Law Gordon Moore: co-founder of Intel Predicted that the number of transistors per chip would grow exponentially (double every 18 months) Exponential improvement in technology is a natural trend: e.g. Steam Engines - Dynamo - Automobile

The Rise of Reconfigurable Systems Moore’s Law The Rise of Reconfigurable Systems 26 December 2018 26 December 2018 Nick Tredennick Nick Tredennick

The Cost of Fabrication Current cost $2 - 3 billion Typical fab line occupies 1 city block, employees a few hundred employees Most profitable period is first 18 months to 2 years For large volume IC’s packaging and testing is largest cost For low volume IC’s, design costs may swamp manufacturing costs

Programmable Logic Devices PLDs Programmable Logic Devices (PLD) General purpose chip for implementing circuits Can be customized using programmable switches Main types of PLDs PLA PAL ROM CPLD FPGA Custom chips: standard cells, sea of gates

PLD as a Black Box (logic variables) (logic functions) Logic gates and programmable switches Inputs (logic variables) Outputs (logic functions)

Programmable Logic Array (PLA) Use to implement circuits in SOP form The connections in the AND plane are programmable The connections in the OR plane are programmable f 1 AND plane OR plane Input buffers inverters and P k m x 2 n

Gate Level Version of PLA 1 P 2 x 3 OR plane Programmable AND plane connections 4 f1 = x1x2+x1x3'+x1'x2'x3 f2 = x1x2+x1'x2'x3+x1x3

Customary Schematic of a PLA 1 P 2 x 3 OR plane AND plane 4 f1 = x1x2+x1x3'+x1'x2'x3 f2 = x1x2+x1'x2'x3+x1x3 x marks the connections left in place after programming

Limitations of PLAs PLAs come in various sizes Typical size is 16 inputs, 32 product terms, 8 outputs Each AND gate has large fan-in  this limits the number of inputs that can be provided in a PLA 16 inputs  316 = possible input combinations; only 32 permitted (since 32 AND gates) in a typical PLA 32 AND terms permitted  large fan-in for OR gates as well This makes PLAs slower and slightly more expensive than some alternatives to be discussed shortly 8 outputs  could have shared minterms, but not required

Programmable Array Logic (PAL) Also used to implement circuits in SOP form The connections in the AND plane are programmable The connections in the OR plane are NOT programmable f 1 AND plane OR plane Input buffers inverters and P k m x 2 n fixed connections

Example Schematic of a PAL 1 P 2 x 3 AND plane 4 f1 = x1x2x3'+x1'x2x3 f2 = x1'x2'+x1x2x3

Comparing PALs and PLAs PALs have the same limitations as PLAs (small number of allowed AND terms) plus they have a fixed OR plane  less flexibility than PLAs PALs are simpler to manufacture, cheaper, and faster (better performance) PALs also often have extra circuitry connected to the output of each OR gate The OR gate plus this circuitry is called a macrocell

Multi-Level Design with PALs f = A'BC + A'B'C' + ABC' + AB'C = A'g + Ag' where g = BC + B'C' and C = h below D Q Clock Sel = 0 En = 0 1 Select En = 1 A B h g f

ROM A ROM (Read Only Memory) has a fixed AND plane and a programmable OR plane Size of AND plane is 2n where n = number of input pins Has an AND gate for every possible minterm so that all input combinations access a different AND gate OR plane dictates function mapped by the ROM

4x4 ROM 22x4 bit ROM has 4 addresses that are decoded -to-4 decoder a 3 d 2 1 -to-4 decoder a

Programming SPLDs PLAs, PALs, and ROMs are also called SPLDs – Simple Programmable Logic Devices SPLDs must be programmed so that the switches are in the correct places CAD tools are usually used to do this A fuse map is created by the CAD tool and then that map is downloaded to the device via a special programming unit There are two basic types of programming techniques Removable sockets on a PCB In system programming (ISP) on a PCB This approach is not very common for PLAs and PALs but it is quite common for more complex PLDs

CPLD Complex Programmable Logic Devices (CPLD) SPLDs (PLA, PAL) are limited in size due to the small number of input and output pins and the limited number of product terms Combined number of inputs + outputs < 32 or so CPLDs contain multiple circuit blocks on a single chip Each block is like a PAL: PAL-like block Connections are provided between PAL-like blocks via an interconnection network that is programmable Each block is connected to an I/O block as well

Structure of a CPLD PAL-like block I/O block Interconnection wires

Internal Structure of a PAL-like Block Includes macrocells Usually about 16 each Fixed OR planes OR gates have fan-in between 5-20 XOR gates provide negation ability XOR has a control input D Q PAL-like block

Programming a CPLD CPLDs have many pins – large ones have > 200 Removal of CPLD from a PCB is difficult without breaking the pins Use ISP (in system programming) to program the CPLD JTAG (Joint Test Action Group) port used to connect the CPLD to a computer

Example CPLD Use a CPLD to implement the function f = x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7

Comparison Flexibility Speed ASIC Very High Very Long Impossible FPGA Technology Performance/ Cost Time until running Time to high performance Time to change code functionality ASIC Very High Very Long Impossible FPGA Medium Long ASIP/ DSP High Generic Low-Medium Very Short Not Attainable Very Short Flexibility Speed