DOR <-> DOM Communication A Short Overview & Test Results K.-H. Sulanke DESY Zeuthen 12/27/2018 K.-H. Sulanke

Contents OSI Model DOR Block Diagram Packet Presentation Control and Data Bytes Bit Encoding / Decoding Status Next Steps I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. 12/27/2018 K.-H. Sulanke

OSI (Open System Interconnect) 7-Layer Model Layer 2 by DOR firmware Physical Layer: 140 Ω twisted pair cable DSUB-9 connector … Data Link: UART like protocol Half Duplex Master / Slave 7 Application 6 Presentation 5 Session 4 Transport 3 Network 2 Data Link 1 Physical I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. 12/27/2018 K.-H. Sulanke

DOR, Block Diagram Altera FPGA EP20K200E PCI Bus Data Buffer P C I - SRAM 2 x 256Kx16 Cable Interface #1 Cable Interface #2 Cable Interface #3 Cable Interface #4 P C I - o r e FLASH 1M x 8 Altera PLD EPM7064 Config JTAG Altera FPGA EP20K200E PCI Bus DOM 1..4 Clock 96 V DOM 5..8 2 2 2 2 Reload I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. 12/27/2018 K.-H. Sulanke

Cable Interface Scheme FPGA ADC 10 Bit PREAMP 10 Cable Con. +96V -96V RS485 DAC 8 Bit 8 alternative use I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. 12/27/2018 K.-H. Sulanke

Rx / Tx Data Path, one Wire Pair PCI Bus FPGA Comm. DAC Framing, Encoding Tx_FIFO_A,B 32 8 8 Data_out Data_in Cable Con. Empty AlmEmpty ReadEna WriteEna Address Decoder 2 Wire Pair Control (8) State Machines BusCycle 4 2 Message_rcvd Interrupt Control 1 Interrupt Diff. Rec. Comm. ADC DeFrame, Decoding Rx_FIFO_A,B 10 8 I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. Data_in Data_out AlmFull Empty WriteEna ReadEna Internal FIFOs will be replaced by external SRAM 12/27/2018 K.-H. Sulanke

User_Defined: not relevant for hardware Packet Header User_Defined Packet_Type Packet_Length 31 24 23 16 15 Packet_Length: 0…65535, amount of bytes to be transferred Packet_Type: Encoding Packet_Type 0x00 Data Packet (standard) 0x01 Time Calibration Data User_Defined: not relevant for hardware I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. 12/27/2018 K.-H. Sulanke

Green = Control bytes added by firmware Packet Presentation Example: Sending 7 bytes to DOM_B 32 bit Tx Buffer Cable Header AB000007 1. Dataword 44332211 2. Dataword 00776655 85 Start_Of_Frame AB 00 07 00 User_Defined Packet_Type Packet_Length_L Packet_Length_H 11 22 33 44 1. Dataword 55 66 77 2. Dataword xx Packet_Number 88 End_Of_Frame I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. incremental number to detect lost packets Green = Control bytes added by firmware 12/27/2018 K.-H. Sulanke

Byte Encoding Data Byte Control Byte 1 2 3 4 5 6 7 8 9 Start Data bits 1 2 3 4 5 6 7 8 9 Start Data bits Stop Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Control Byte 1 2 3 4 5 6 7 8 9 Start Address Command Odd Par. Tag Stop Adr0 Adr1 Cmd0 Cmd1 Cmd2 Cmd3 x I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. Odd Parity of Adr0..1, Cmd0..3 12/27/2018 K.-H. Sulanke

Commands Not used 0000 STF 0001 X Start Of Frame EOF 0010 End Of Frame Encoding CMD3..0 Used by DOR Used by DOM Description Not used 0000 STF 0001 X Start Of Frame EOF 0010 End Of Frame IDREQ 0011 DOM ID Request, needed ? 0100 DRREQ 0101 Data Read Request (data polling) DRAND 0110 Data Read Acknowledge, No Data aval. DRBT 0111 DOM Rebooting MRWB 1000 Message Received With (more) Buffer MRNB 1001 Message Received No (more) Buffer MRWE 1010 Message Received With Error COMRES 1011 (DOM~) Communication Reset BFSTAT 1100 (DOM~) Buffer Status request SYSRES 1101 (DOM~) System Reset (Soft Boot) TCAL 1110 Time Calibration cycle follows IDLE 1111 IDLE, DOM answer on COMRES or IDLE I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. 12/27/2018 K.-H. Sulanke

Command Sequence DOR DOM Description (only one DOM is connected) COMRES .. IDLE After power on the DOR sends every 2 ms a COMRES until DOM sends an IDLE back. DRREQ DRAND Data Read Request. The DOM has no data. STF … EOF MRNB Start Of Frame, Data, End OF Frame. The DOR was sending a packet The DOM received error free, but has no more buffer BFSTAT Buffer Status Request. The DOM still has no buffer. Data Read Request. The DOM is responding with a packet. MRWB Buffer Status Request. DOM buffer is available now DRBT Data Read Request. The DOM is rebooting now. DOM is rebooting. The DOR sends every 2 ms a COMRES . DOM is ready now (typical after 160ms). I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. 12/27/2018 K.-H. Sulanke

DOM Reboot Problem After DOM power on the DOM is rebooting two times Every reboot means a FPGA-reload as well Problem: asynchronous loss of communication Solution: synchronization with the data polling, DOM may only reboot after answering on DRREQ with DRBT DOR stops all data transfer and sends COMRES until it gets an IDLE back I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. 12/27/2018 K.-H. Sulanke

Tested Functionality Power On synchronization (COMRES command) DOM A/B data polling (DRREQ, DRAND) Framing and Deframing (STF, EOF) Prevention of DOM buffer overrun (BFSTAT, MRNB, MRWB) DOM Reboot handling (DRBT command) Automatically detection of a missing DOM -> full bandwidth dedicated to the other one SYSRES and TCAL not yet tested I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. 12/27/2018 K.-H. Sulanke

Data Encoding DC-free bit encoding, 1MBit/s “0” = quiet line, “1” = bipolar rectangular pulse, T=1µs Tx (DAC) and Rx Signal using the new Ericsson Cable (3.4 km) 1001111011…. HL_edge > 30 mV I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. Measured between GND and one transformer tap using a Tektronix standard probe 12/27/2018 K.-H. Sulanke

Digital Decoding evaluating the HL-edge in a time window to detect a “1” baseline correction not necessary 01001110 Start Stop 72hex Start point dU dt Stop point I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. 12/27/2018 K.-H. Sulanke

Noise problem: missing of a “standard” noise source noise by neon lamp starters and electrical engines used to evaluate the design progress noise caused by a neon table lamp, measured at the preamp’s out I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. 12/27/2018 K.-H. Sulanke

Digital Filtering simple digital mean value calculation over 4 ADC samples (bit time is 20 samples) mean(adc[9..0])i = (adc[9..2]i-1 + adc[9..2]i-2 + adc[9..2]i-3+ adc[9..2]i-4) lower two bits not used, 0..3 -> 0..3mV goal is to eliminate high frequency noise spikes the filter algorithm is limited by the available FPGA resources Test using “natural” noise sources have shown a significant improvement more data security by decoding the stop bit only if the stop bit has arrived the byte is written to the Rx FIFO prevents zero bytes, caused by single noise spike-“start bits” I would like to present you two examples of fast link interfaces, designed in our lab. For both cards block schemes, test results and conclusions will be presented. 12/27/2018 K.-H. Sulanke

Status long term DOS-test with 4 DOMs (2 days, 3.4km new Ericsson cable, 48KB/s/DOM) error free under lab conditions DOM-Reboot needs still some debugging DOM Soft Boot (command SYSRES) still has to be tested Time calibration (command TCAL) not yet implemented 12/27/2018 K.-H. Sulanke

Next Steps DOM Soft Boot (command SYSRES) and TCAL test Debug FIFO to record the last 256 control bytes Possible improvements: Adaptive edge decoder, especially for the DOM side (pk-pk value changes from 60mV to 1.2V, when a DOM is responding, but the other one is receiving) Automatic adaption of the communication threshold after DOM power on 8b/10b encoding scheme for better signal/noise ratio and/or higher data rates 32 bit checksum implementation Hardware initiated retransmit in case of an error 12/27/2018 K.-H. Sulanke