تراشه ها ي منطقي برنامه پذ ير

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Presentation transcript:

تراشه ها ي منطقي برنامه پذ ير مرتضي صاحب الزماني

چرخه ي طراحي براي FPLDها Design Entry Schematic Netlist HDL Waveform State Diagram مرتضي صاحب الزماني

Textual or Schematic Most people today use textual languages (like VHDL or Verilog) rather than schematic for most digital design. Schematics make poor use of screen space. Not appropriate for large designs. Easier tooling (parsing). مرتضي صاحب الزماني

FPGA Placement & Routing مرتضي صاحب الزماني

Field Programmable Gate Array (FPGA) مرتضي صاحب الزماني

چرخه ي طراحي براي FPLDها کوتاه شدن پروسه ي طراحي. مزايا: نوآوري بيشتر (پروسه ي طراحي به مراحل بالاتر رفتاري منتقل مي شود) (تشابه با زبانهاي سطح بالا) Debug طرح بسيار آسانتر و سريعتر. مانند سيکل برنامه نويسي: کامپايل اجرا برنامه نويسي ويرايش کامپايل شبيه سازي ورود طرح ويرايش سنتز تغييرات در طرح بسيار آسانتر. بعضي شرکتها نسخه هاي جديد سخت افزار خود را روي CD يا از طريق اینترنت در اختيار مشتري خود قرار مي دهند تا EPROM را مجددا برنامه ريزي کند. مرتضي صاحب الزماني

Productivity Gap Moore's Law: Productivity of designers: Our ability to manufacture logic transistors: ~ 58% per year. Productivity of designers: Their ability to design and implement correct and testable transistors per staff-month: < 25% per year. مرتضي صاحب الزماني

Design Productivity Gap 1981 leading edge chip required 100 man-months 10,000 transistors / 100 transistors/man-month 2002 leading edge chip requires 30K man-months 150,000,000 / 5000 transistors/man-month Designer cost increase from $1M to $300M مرتضي صاحب الزماني

مقايسه ي FPLD و ساير سبکها سرعت: چند صد MHz : بسيار بالاتر از سيستمهاي SSI-based اما کمتر از ASIC و Custom (حدود 3-4 برابر) Ian Kuon , Jonathan Rose, “Measuring the gap between FPGAs and ASICs,” FPGA, 2006. علت کندي: اتصالات برنامه پذير  مقاومت و خازن دانسيته: کمتر از ASIC (حدود 40/1 يا 20/1) مرتضي صاحب الزماني

مقايسه ي FPLD و ساير سبکها توان مصرفي: بيشتر از ASIC (حدود ده برابر) زمان توسعه: FPLD: prototyping و شبيه سازي با استفاده از Toolها (چند روز و هفته) ASIC: ساخت maskها، ساخت ويفر، packaging، Testing بسيار وقت گير (چند ماه) مرتضي صاحب الزماني

مقايسه ي FPLD و ساير سبکها Prototyping : در FPLD به سرعت مي توان نمونه اوليه را توليد کرد: Time-to-Market بعضي از شرکتها نسخه Mask Programmed را به مشتري عرضه مي کنند. هزينه ي تست: در FPLD کاربر مجبور نيست براي هر طرح، IC را تست کند. مرتضي صاحب الزماني

مقايسه ي FPLD و ساير سبکها تغيير در طرح : FPLD را مي توان به طور الکتريکي در چند ميلي ثانيه (تا دقيقه) customize کرد. ASIC نياز به custom mask چند هزار دلاري دارد (براي توليد بسيار بالا قابل توجيه است). Inventory Risk: در ASIC بايد ميزان نياز بازار به دقت ارزيابي شود (بيش از حد يا کم توليد نشود) اما FPLD مانند SSI و MSI استاندارد براي نيازهاي عام قابل استفاده است. مرتضي صاحب الزماني

مقايسه ي FPLD و ساير سبکها هزينه: مسايل بالا در هزينه تاثير دارند. ASIC براي تعداد بسيار بالا مقرون به صرفه است. FPLD از نظر طراحي و تغيير در طرح مقرون به صرفه است. Tooling Testing NRE (Non-Recurring Engineering Cost ) اوليه: ASIC چندصد هزار دلار (طراحي، توليد ماسکها، توسعه ي تست)  انتخاب بين FPLD و ASIC بستگي به کاربرد و حجم توليد دارد. مرتضي صاحب الزماني

مقايسه ي FPLD و Custom Logic Semi-/Full-Custom Logic Requirement FPLD Discrete Logic Speed Density Cost Prototype Manufacturing Future Modification Inventory Development Tool Very Effective Adequate Poor مرتضي صاحب الزماني