5G Timing - Customers Deployments SyncSmart 2018
EU Tier 1 customer #1 : Full on Path support Timing Transport Architecture
Tier 1 customer: 5G DWDM Timing Architecture (<130ns) 13.08.2007 Autor / Thema der Präsentation 3 T - BC D Site 2 WEST Core Site 1 ET 7IVV Site 3 Site 4 Site 5 Site 6 OADM 7IV9 Site 7 EAST Core Site 8 Measurement OLA UZ04 W O Multi-band GNSS 57,31 km 46,96 km 59,24 km 47,10 km 21,82 km 31,90 km 80,46 km ePRTC GM Cs TS3550 TP4100 ToD interface (RS422 bei NSO bereits vorhanden Bi-Di SFPs (single strand) to minimize asymmetry G.8275.1, L2 Full-On-Path Support profile OADM drops specific Lambdas for Sync (two wavelengths) ePRTC to minimize timing error T-BC Class D (<5ns) – TP4100
Core Site Detailed Architecture 13.08.2007 Autor / Thema der Präsentation 4 TP4100
Transport Site Detailed Architecture 13.08.2007 Autor / Thema der Präsentation 5 M S 1GE el. (RJ45) (PTP-FTS/SyncE) + Management 1 2 3 4 5 6 W O AGS/xy #1 #2 #3 #4 SSU- 2000E 4*SFP 4*SFP+ #5 #12 ………………………………………… T-BC Class D needed cTE<5 ns OCXO
NA Tier 1 customer : VRAN network without on-path support.
Network Setup with TP4100 Slave TC14
TC14 TP4100 Slave Results First 18 hours of Reference Client with 3 HOP TC14 Traffic Loading on Verizon 3 Hop Mobile Backhaul Demo Network. Started with none loaded connection and the TC 14 traffic load started nominally 1 hour into test window.
TC14 TP4100 Slave Results The graph below shows the cumulative time error distribution of the reference client. The 90% performance is within 100ns dynamic accuracy under the TC14 3 Hop Test condition.
Static 40%30% and TC14 TP4100 Slave Results First 18 hours of Reference Client with 2 HOP TC14 Traffic on 10G links and 40-30 Loading on 1G links to see contribution of the 1G portion to time accuracy.
Static 40%30% and TC14 TP4100 Slave Results The dynamic accuracy under this test is now 50ns with 90% confidence. This shows that half of the accuracy budget is consumed by the 7750 operating with TC14 dynamic load tests.
Thank You Eran Gilat – Systems Architect Engineer FTD eran Thank You Eran Gilat – Systems Architect Engineer FTD eran.gilat@microsemi.com