MLWG - User Requirements

Slides:



Advertisements
Similar presentations
Database System Concepts and Architecture
Advertisements

by Adiel Khan Staff CAE Synopsys
Software Engineering For Beginners. General Information Lecturer, Patricia O’Byrne, office K115A. –
Lecture Nine Database Planning, Design, and Administration
TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective.
SOA – Development Organization Yogish Pai. 2 IT organization are structured to meet the business needs LOB-IT Aligned to a particular business unit for.
Introduction to the Enterprise Library. Sounds familiar? Writing a component to encapsulate data access Building a component that allows you to log errors.
Chapter 9 Database Planning, Design, and Administration Sungchul Hong.
-Nikhil Bhatia 28 th October What is RUP? Central Elements of RUP Project Lifecycle Phases Six Engineering Disciplines Three Supporting Disciplines.
THE GITB TESTING FRAMEWORK Jacques Durand, Fujitsu America | December 1, 2011 GITB |
ITEC224 Database Programming
1CADENCE DESIGN SYSTEMS, INC. Cadence Proposed Transaction Level Interface Enhancements for SCE-MI SEPTEMBER 11, 2003.
SystemC: A Complete Digital System Modeling Language: A Case Study Reni Rambus Inc.
Enterprise Java Beans Java for the Enterprise Server-based platform for Enterprise Applications Designed for “medium-to-large scale business, enterprise-wide.
2Object-Oriented Analysis and Design with the Unified Process The Requirements Discipline in More Detail  Focus shifts from defining to realizing objectives.
1 Integration Verification: Re-Create or Re-Use? Nick Gatherer Trident Digital Systems.
EDA Standards – The SPIRIT View Gary Delp VP and Technical Director SPIRIT.
© 2012 xtUML.org Bill Chown – Mentor Graphics Model Driven Engineering.
Advanced Computer Networks Topic 2: Characterization of Distributed Systems.
The Macro Design Process The Issues 1. Overview of IP Design 2. Key Features 3. Planning and Specification 4. Macro Design and Verification 5. Soft Macro.
Boost Verification Results by Bridging the Hw/Sw Testbench Gap by Matthew Ballance Verification Technologist Mentor Graphics.
Distribution and components. 2 What is the problem? Enterprise computing is Large scale & complex: It supports large scale and complex organisations Spanning.
Sept 13-15, 2004IHE Interoperability Workshop 1 Integrating the Healthcare Enterprise Patient Identifier Cross-referencing Charles PARISOT GE Healthcare.
Discussion of ITC Goals. Historical Goals From SCE-API Marketing presentation Circa 2001.
Workforce Scheduling Release 5.0 for Windows Implementation Overview OWS Development Team.
Architecture View Models A model is a complete, simplified description of a system from a particular perspective or viewpoint. There is no single view.
Test Plan: Introduction o Primary focus: developer testing –Implementation phase –Release testing –Maintenance and enhancement o Secondary focus: formal.
D. Duellmann - IT/DB LCG - POOL Project1 The LCG Dictionary and POOL Dirk Duellmann.
Discussion of ITC Goals. Historical Goals From SCE-API Marketing presentation Circa 2001.
ISCUG Keynote May 2008 Acknowledgements to the TI-Nokia ESL forum (held Jan 2007) and to James Aldis, TI and OSCI TLM WG Chair 1 SystemC: Untapped Value.
Viewpoint Modeling and Model-Based Media Generation for Systems Engineers Automatic View and Document Generation for Scalable Model- Based Engineering.
April 15, 2013 Atul Kwatra Principal Engineer Intel Corporation Hardware/Software Co-design using SystemC/TLM – Challenges & Opportunities ISCUG ’13.
Design Engineering 1. Analysis  Design 2 Characteristics of good design 3 The design must implement all of the explicit requirements contained in the.
OrbEEt Project Introduction <Location>, <Date> Presenter
CIS 375 Bruce R. Maxim UM-Dearborn
The Post Windows Operating System
Rapid Launch Workshop ©CC BY-SA.
CCNA Routing and Switching Routing and Switching Essentials v6.0
Integrating HA Legacy Products into OpenSAF based system
INCOSE Usability Working Group
Self Healing and Dynamic Construction Framework:
Complexity Time: 2 Hours.
Introduction to Triggers
Distribution and components
EOB Methodology Overview
Chapter 10: Device Discovery, Management, and Maintenance
CCNA Routing and Switching Routing and Switching Essentials v6.0
Introduction to J2EE Architecture
TIM 58 Chapter 8: Class and Method Design
Description of Revision
Timothy Pertuit, David Lacey, Doug Gibson
Dev Test on Windows Azure Solution in a Box
Thank you for joining. This presentation will begin shortly.
Chapter 2 Database Environment Pearson Education © 2009.
Chapter 10: Device Discovery, Management, and Maintenance
Starting Design: Logical Architecture and UML Package Diagrams
Analysis models and design models
Course: Module: Lesson # & Name Instructional Material 1 of 32 Lesson Delivery Mode: Lesson Duration: Document Name: 1. Professional Diploma in ERP Systems.
Verilog-AMS Integration with P1800 SV Standard
Chapter 2: Operating-System Structures
Teneo Ganymede Simultaneous Release Graduation Review
The Anatomy and The Physiology of the Grid
Design Yaodong Bi.
ITAS Cash Management Integration to an ERP
Chapter 2 Database Environment Pearson Education © 2009.
Chapter 2: Operating-System Structures
Chapter 2 Database Environment Pearson Education © 2009.
Design.
ONAP Architecture Principle Review
Implementation Plan system integration required for each iteration
Presentation transcript:

MLWG - User Requirements ML User-companies WG Nov 6, 2012

MLWG – Agenda 2 Month day, 2012 Problem Statement Representation Motivations/Goals Representation Overview High-level Requirements Proposed Architecture Key Requirements Initialization and Configuration Synchronization Phasing Communication Implementation Recommendations Next Steps and Plan of Action

MLWG – Problem Statement 3 Month day, 2012 MLWG – Problem Statement There is no standardized or ubiquitous way to integrate both verification IP and other design or verification collateral in different frameworks/languages to create a simulation model. The scope of this problem includes simulation, emulation, and acceleration.

MLWG – Motivations/Goals 4 Month day, 2012 MLWG – Motivations/Goals Why a standard is required in this space The need to develop products that involve integrating IP from multiple providers is rapidly growing and requires standards to do this more efficiently. Existing standards require a path towards interoperability with newer standards. Accellera needs to align their own standards development. Initial Working Group Goal Collect the user-level requirements of a solution that can solve this problem and make a recommendation for the next steps, including organizational aspects, to address the ML challenge.

MLWG – Representation Chair: Warren Stapleton 5 Month day, 2012 MLWG – Representation Chair: Warren Stapleton There have been 20 weekly 2hr meetings + 2 cancelled time slots. Data extracted from minutes:

MLWG – Use-cases Considered 6 Month day, 2012 MLWG – Use-cases Considered The two main use-cases used for discussion: A transactor sitting in one framework/language being used in another framework/language to provide monitored transactions to a scoreboard. A behavioral model in one framework/language being used as a predictor of behavior for a scoreboard in another framework/language.

MLWG – High-level Requirements Portable Must provide vendor neutrality for user-level code (Stimulus, Transactors, Scoreboards) Easy to use User-level verification-IP code must not be made aware of the mixed-language solution Provide a natural use model for existing methodologies (UVM, SystemC, …) Leverage existing standards where possible Frameworks must be able to operate without the mixed-language solution if they are the only framework being used Useful Must enable the concept of reusable verification-IP Must allow for development of interoperable solutions with proprietary frameworks Must provide standard APIs for framework facilities like: Startup, Messaging, Configuration, Synchronization (timing and phasing), Communication, Shutdown Available Working group must deliver a prototype

MLWG – Proposed Architecture 8 Month day, 2012 MLWG – Proposed Architecture

MLWG – Requirements for Configuration Any framework should be able to participate in a logical hierarchy concept. Need to have top level logical hierarchies that can start in any framework. Provide persistency of configuration data beyond configured model usage, e.g. post processing. Provide access API for typed configuration data. API will provide capability to insert and retrieve configuration data, that will fail compilation if not type correct. Provide a performance/memory consumption optimized storage method of configuration data that is accessible across frameworks. Implementation detail is whether it is centralized or distributed. Provide override capability based on logical hierarchy to enable configuration based build. provide a scope/content/logical hierarchy based approach to configuration data identification. Provide capability to pass configuration data from the simulation command line. Accessing (storing/retrieving) configuration data should not be dependent on the existence of a specific framework. Configuration can be used for managing resource data in addition to configuration data. For simplicity we are naming this the configuration package but it is good for resources as well.

MLWG – Synchronization Requirements Enable key synchronization methods across frameworks Provide a uniform mechanism for synchronizing time Provide APIs for registering/connecting standard UVM Methodology synchronization primitive styles as a minimum foundation such as: Events Objections Barriers Time synchronization Provide a time notification service for adapters to schedule wakeups Multiple concurrent notifications at different intervals can be specified One or more adapters can register with one or more notifications Synchronize the view of a clock domain across multiple frameworks Synchronization Methods Notifications shall be with or without transmittable data

MLWG – Phasing Requirements Shall be only one master phase control mechanism provided Provide phase notifications for all phase related activity Enable framework phase responses to notifications Enable frameworks to post phase requests independent of notifications Default to UVM predefined phase schedule, if none provided Ability to map controller phase names to local framework phase names Pre-run, post-run synchronization across frameworks Minimal: Pre-run synchronization at end of elaboration(barrier/notification) Post-run synchronization at the point the run phase completes Support for either fine-grained or coarse-grained synchronization Notify if pre/post-run phase traversal is top-down or bottom-up Run time phase action notification for participating frameworks Support for registering any schedules and phases at least for runtime Ability for a framework to request a jump to any runtime phase

MLWG – Communication Requirements (1) Requirements Scope Within: Messaging amongst verification components in different frameworks such as transactions and events Outside: Generalizations for config access and phasing Outside: Time synchronization assumed part of synchronization requirements Foundation Shall enable all communication-specific TLM 2.x usage models Shall enable specific TLM 1.x capabilities such as analysis ports Enabling Requirements Shall enable discovery of components and other communication participants Shall enable messages to support all information necessary for routing Shall enable dynamic connectivity changes Shall enable TLM-specific timing synchronization (global quantum)

MLWG – Communication Requirements (2) Execution Requirements Shall enable communicating a single message container data type with serializable contents Shall enable correlation amongst components with maintained message-identity for life time of a message Shall enable one-to-one, one-to-many and many-to-one connectivity Shall enable uni-directional and bi-directional communication Shall enable blocking and non-blocking messaging

MLWG – Implementation requirements Reference implementation Implementation of backplane in C++ and C++ as the second language for the adapters Leverage available industry standards and implementations where possible Fully functional with all major vendor's simulators Examples Examples to demonstrate interoperability and/or interfacing with other languages standards and methodologies including C++, e, SystemC, UVM-SV, VHDL, SCE-MI Test functionality using the UVM-SV framework implementation, getting full coverage on the UVM side Regression suite / tests Set of compliancy tests to validate compatibility with the ML standard interface, functionality and performance

MLWG – Recommendation Restructure Accellera WGs to provide better standards alignment VIP-TSC was primarily purposed with aligning VMM, OVM and providing a System-Verilog solution Examples of poor alignment: UVM and SystemC (CCI) configuration are not aligned and not working together as far as the MLWG is aware of. UVM RAL, IP-XACT registers, and SystemRDL. Currently working on building interoperable solutions out of what exists as opposed to architecting a holistic solution. See initial proposal in next slide Committee to focus on the overall methodology along with sub-committees: VIP-SV library VIP-SC library VIP-Backplane With requirement to support frameworks other than UVM-SV or SystemC Charter of committee (Could be new charter of VIP-TSC) Define a unified methodology that can enable the deployment of UVM methodology in multiple frameworks and allow them to interoperate. Create a standardized VIP-API document.

MLWG – Proposed WG Structure

MLWG – Proposed Group Mapping 1717 Month day, 2012 MLWG – Proposed Group Mapping

MLWG – Next Steps and Plan of Action Phase 1 (2012) Complete the user requirements gathering About 75% done and should be completed before the VIP-TSC F2F Present to the WG Chairs and Solicit Feedback Propose aligned working group structure Phase 2 (2013) Expand and collect vendor requirements Resolve/consolidate user and vendor requirements Propose implementation approach/responsibilities Phase 3 (2013-2014) Implementation/realization of standardized UVM/ML-API Develop some metrics to measure success For example: UVM API alignment