Circuit Characterization and Performance Estimation

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Presentation transcript:

Circuit Characterization and Performance Estimation Chapter 4 Circuit Characterization and Performance Estimation

Effective Resistance and Capacitance In the worst case, there is only one PMOS “ON”. Thus, two unit width have resistance R. R/3

Diffusion Capacitance Layout Effects

Elmore Delay Model

Example Tpdr=R*((6+4h)C) Tpdf=R/2*2C+R*((6+4h)C)

Logical Effort Logical effort: The ratio of the input capacitance of the gate to the input capacitance of an inverter HW: EXERCISE 4.19

3 units of diffusion capacitance on the output, defined 1 Parasitic Delay 3 units of diffusion capacitance on the output, defined 1 6 units of diffusion capacitance on the output, normalized with INVERTER

Gate-Source Capacitance Tpdf=R/2*(2C+2C)+R*((6+4h)C)

f=g (logical effort)*h Linear Delay Model d (propagation delay) =f (stage effort)+p (parasitic delay) f=g (logical effort)*h h=4/1 h=Cout/Cin d=gh+p=1* 4 +1 =5 HW: EXERCISE 4.21 HW: EXERCISE 4.5

Delay in multistage Logic

Example

Example G=1*1=1 H=90/5=18 F=f1*f2=g1h1*g2h2 =1*(90/15)*1*(90/15) =36 b=(15+15)/15=2

Example B=3*2=6 G=(4/3)*(5/3)*(5/3)=100/27 H=45/8 F=BGH=125 P=2+3+2=7 The best stage effort =^f=1251/3=5 D=N (N-stage)*^f+P =3*5+7=22 y=Cout*g/^f=45*(5/3)/5=15 x=Cout*g/^f=(15+15)*(5/3)/5=10 A=Cout*g/^f=(10+10+10)*(4/3)/5=8

Example 10 15 8 y=Cout*g/^f=45*(5/3)/5=15 x=Cout*g/^f=(15+15)*(5/3)/5=10 A=Cout*g/^f=(10+10+10)*(4/3)/5=8

Choosing the Best Number of Stages P=N*1 B=1 H=64/1=64 G=1 F=BGH=64 The best stage effort =^f=F1/N=641/N D=N*^f+P HW: EXERCISE 4.10

Best Number of Stages Let After iteration, the best stage effort is e (2.71828). HW: EXERCISE 4.24 (ρ=4)

Pstatic_total=130 W*(31+24)=7.2 mW Static Dissipation Example =73 A =130 W Pstatic_total=130 W*(31+24)=7.2 mW Pstatic=IstaticVDD

Dynamic Dissipation Pdynamic=*α*CVDD2fsw Activity factor Example Clogic= 24 nF, Cmemory= 72 nF Example Pdynamic_total=(0.1*24n+0.05*72n)*1.22 =8.6 mW/MHz = 8.6 W @1GHz HW: EXERCISE 4.27

Power Reduction Device-switching capacitance is reduced by choosing small transistors. Choosing a lower power supply significantly reduced power supply. Clock gating can be used to stop portions of the chip that are idle. Reducing leakage current when the chip is idle. HW: EXERCISE 4.28

Resistance

Capacitance Cgnd=Cbot+Ctop Ctotal=Cgnd+2Cadj

Delay Example 5mm long,0.32 um wide metal2 5000/0.32=15625  15625  * 0.05 /=781  0.2fF/m * 5000 m=1 pF HW: EXERCISE 4.30

Inductance

Reduce Inductance

Wire engineering Width and spacing Layer selection Shielding Repeaters

Pitches and Spacings

Low-resistance layer for fast and critical signals is chosen. Layer selection Low-resistance layer for fast and critical signals is chosen.

Shielding Very sensitive signals such as clock and analog signals must be shieled.

Repeaters

Crosstalk

Reduce crosstalk

Design Margin Supply voltage (10%) Operating temperature Process variation

Design Corners

Latchup A larger current flowing between VDD and GND that persists until the power supply is turned off or the power wires melt. Minimize Rsub and Rwell to prevent latchup

Scaling

Scaling MOS Devices

Romap of Predictions