Introduction to 3D NAND Dec 1st, 2011 Semiconductor

Background of 3D NAND Contents 3D NAND Technology 3D Development Status & Schedule

Scaling Limitation in Floating Gate _ Process High Aspect Ratio of Gate Stack  WL Leaning Narrow Space between F/Gs  IPD Leakage, C/G Depletion J.D. Choi, IMW2010 Short Course

Scaling Limitation in Floating Gate _ Interference Cell to Cell interference reach to 50% of FG capacitance at 15~16nm.  Narrow Read Window Margin 100 % ● Total ● W/L –W/L ● B/L – B/L ● Diagonal 10 % 1.0 % 0.1 % 100 10 Technology Node [nm] K.Prall, et al, NVSMW 2007, pp 26-30

3D NAND Technology Contents Introduction to 3D NAND 3D Development Status & Schedule

3D Cell (Vertical String) Key Feature 2D Cell 3D Cell (Vertical String) D ONO channel CG FG channel CG S D Well S Single crystal Si channel Floating Gate 1-side gate Channel-first process 2 step litho (ISO/Gate) Poly-Si channel SONOS All-around gate Channel-last process 1 step litho (hole)

= = 3D : Rotation of 2D Rotation 2D Planar String NAND Flash CHANNEL BL = Rotation 3D Vertical String NAND Flash BL =

Schematic diagrams & TEM images 3D NAND Cells DC-SF (Hynix) P-BiCS TCAT Complicated Fast Erase Slow erase No Charge Spreading Charge Spreading Possible Difficult Schematic diagrams & TEM images Process Erase Speed Data retention MLC DC-SF : Dual Control-gate with Surrounding Floating- gate(1) P-BiCS : Pipe-shaped Bit Cost Scalable (2) TCAT : Tera-bit Cell Array Transistor(3) (1) Sung Jin Whang, et al, IEDM. 2010, pp.668-671 (2) Katsumata, R. et al., VLSI Technology, 2009 pp.136-137. (3) Won-seok Cho, et al., VLSI Tech.2010, pp.173-174,

Key Issues in 3D NAND _ Complicated Process P BiCs Process Slimming & SG hole open PC formation Sac Material Dip-out & ONO/poly filling Stack + Channel hole formation Metallization Select Gate formation

Key Issues in 3D NAND _ Poly Si Channel Long Poly-Si channel  Low Cell Current, Wider Vth Distribution

Key Issues in 3D NAND _ Slow Erase Speed Electrons back tunneling from C/G to charge trap layer  Erase Vth Saturation Top oxide with High K material ( Al2O3) and gate material with large work function have been studied, however, insufficient in erase speed Back tunneling e e Discharging Gate SiO2 SiN SiO2 Si sub

3D Development Status & Schedule Contents Introduction to 3D NAND 3D NAND Technology 3D Development Status & Schedule

Hynix’s New 3D NAND Cell _ DC – SF Cell Hynix ‘s own F/G type 3D NAND cell, Dual CG –Surrounding FG Cell F/G is adopted and controlled by two Control Gates.  Fast Erase Speed, No Charge Spreading, No Interference Sung Jin Whang, et al, IEDM. 2010, pp.668-671

DC-SF _ Cell Cross Sectional View Cell String Single Cell

DC-SF Cell _ Program/Erase Speed Program / Erase speed is comparable to 2D NAND Cell

DC-SF Cell _ No Charge Spreading In SONOS type 3D NAND, stored charges spread through connected SiN layer No Charge migration in separate F/G type DC-SF Cell

DC-SF Cell _ No Interference Separated F/G in DC-SF Cell  No interference in DC-SF Cell 3D DC-SF Cell 2D Planar F/G Cell

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