Garimella Srinivas Gottiparthy Ramraj Vippa Prakash Robust Path Delay Test Garimella Srinivas Gottiparthy Ramraj Vippa Prakash

CONTENTS Introduction Path Count Algorithm Critical Path Detection Robust path delay test with 5-valued logic Conclusion Demo and Questions

Introduction Delay Test : A circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing. Fault Models Gate Delay Fault Model Path Delay Fault Model Path Count Critical Path – Longest Delay Combinational Path.

Path Count Algorithm Path Count = 8 1 A 1 3 B F 1 G J 1 2 L 3 C K E H D Path Count = 8

Critical Path Detection 1 B L H 2 I O 3 1 Q C F P J 2 K 1 D G M 2 R E N

Robust Path Delay Test And / Nand Or/ Nor Rising (U1) U1 S0 Gate Transition And / Nand Or/ Nor Rising (U1) U1 S0 Falling (U0) S1 U0 A 1 B S1 2 S1 3 Q 1 U0 C F U0 S1 U0 2 U0 E 1 D G U0 2 R

Robust Path Delay Test G1 s-a-0 G2 s-a-0 S1 S1 3 Q U0 C U0 S1 U0 2 U0

Conclusion Achievements Improvements Better understanding of Hitec tool. Improvements Implement an Algorithm to determine Vectors. Implement Non-Robust test in case robust test fails.

Demo And Questions