Digital Systems Design 2 VHDL Basic Language Concepts Ref. “VHDL Starter’s Guide”, Sudhakar Yalamanchili, Prentice Hall, 1998

VHDL – Basic Language Concepts VHDL will be presented as a tool for describing attributes of digital systems such as: Events, Propagation Delays, Concurrency, and Waveforms. Concepts will be introduced next that will extend basic constructs already presented that would enable development of application of conventional programming in building models of complex digital systems, particularly at higher level of abstracton. 31 December 2018 Veton Këpuska

Signals Conventional programming languages manipulate basic objects such as variables and constants. Variables receive values through assignment statements and can be assigned new values through the course of a computation. Constants on the other hand may not change their values. In contrast, digital systems are fundamentally about signals. 31 December 2018 Veton Këpuska

Signals Signals are analogous to the wires used to connect components of a digital circuit. Signals make take one of several values such as 0, 1, or Z (high impedance). Those values are defined by IEEE 1164 standard. VHDL introduces a new type of programming object: the signal object type to capture the behavior of digital signals. Signals may be assigned values. They differ from variables in that they have an associated time value, since signal receives a value at a specific point in time. The signal retains this value until it is assigned a new value at a future point in time. The sequence of values assigned to a signal over time constitutes the waveform of the signal. Association of time-value pairs that differentiates a signal from variable. IEEE 1164 Value system Value Interpretation U Uninitialized X Forcing Unknown Forcing 0 1 Forcing 1 Z High Impedance W Weak Unknown L Weak 0 H Weak 1 - Don’t care 31 December 2018 Veton Këpuska

Signals Variables may be declared to be of a specific type: integer, real, or character. Similarly signals can be declared to be of specific type. When used in this way signal does not necessarily have correspondence with the wires that connect digital components. Example: Modeling of the output of ALU can be done as using integer values: Designer does not have to be concerned with modeling the number of bits necessary to model the output of ALU. This behavior of the language enables designers to model systems at a higher level of abstraction than digital circuits. Such approach at high-level simulation is useful in the early stages of the design process, where many details of the design are still being developed. Before introducing details of how to declare and operate signals in VHDL one must first cover the basic programming constructs. 31 December 2018 Veton Këpuska

VHDL: Entity The primary programming abstraction in VHDL is a design entity. Examples of design entities include: Chip, Board, Transistor. Entity is a component of a design whose behavior is to be described and simulated. 31 December 2018 Veton Këpuska

VHDL: Entity External interface in VHDL is defined via the Entity constructs: entity half_adder is port (a, b: in bit; sum, carry: out bit); end half_adder; Half-adder circuit Boldface type denotes keywords that are VHDL reserved words. half_adder is the name given to this design entity. VHDL is case insensitive. Input and outputs of the circuit are referred to as ports. Ports are special programming objects and are signals. Ports are the means by which the half adder can communicate with the external world or other circuits. Thus naturally ports are expected to be signals rather than variables. 31 December 2018 Veton Këpuska

VHDL: Entity entity half_adder is port (a, b: in bit; sum, carry: out bit); end half_adder; Like variables each in conventional languages each port must be a signal that is declared to be of specific type: A bit is a signal type that is defined within VHDL language and can take values of 0 or 1. A bit_vector is a signal type comprised of a vector of signals, each of type bit. The type bit and bit_vector are two common types of ports. All VHDL common data types and operators will be addressed later when appropriate. 31 December 2018 Veton Këpuska

VHDL: Entity entity half_adder is port (a, b: in std_ulogic; sum, carry: out std_ulogic_vector); end half_adder; Signals can take on many different values other then 0 and 1. Thus in practice the types bit and bit_vector are of limited use. IEEE 1164 standard is gaining widespread acceptance as a value system. In this standard the 9-value signal would be declared to be of type std_ulogic rather than bit. Analogously, std_ulogic_vector type would be used instead of bit_vector. 31 December 2018 Veton Këpuska

VHDL: Entity entity half_adder is port (a, b: in std_ulogic; sum, carry: out std_ulogic_vector); end half_adder; The signals appearing in a port declaration may be distinguished as: input signals (in), output signals (out), or bi-directional signals (inout). Every port in the entity description must have its mode and type specified. Groups of signals (buses) can be declared as Vectors. For example a 32 bit quantity is declared to be of the vector type as follows: std_ulogic_vector (31 downto 0) 31 is the most significant bit. And 0 is the least significant bit. 31 December 2018 Veton Këpuska

VHDL: Entity Entity declaration of a 4-to-1 multiplexer: entity mux is port (I0, I1: in std_ulogic_vector (7 downto 0); I2, I3: in std_ulogic_vector (7 downto 0); Sel : in std_ulogic_vector (1 downto 0); Z : out std_ulogic_vector (7 downto 0)); end mux; 4-to-1 Multiplexer: I0 I1 Z I2 I3 Sel 31 December 2018 Veton Këpuska

VHDL: Entity Entity Declaration of a D Flip-Flop entity D_ff is port (D, CLK, R, S: in std_ulogic; Q, Qbar : out std_ulogic); end D_ff; Example of D Flip-Flop: 31 December 2018 Veton Këpuska

VHDL: Entity 32-bit ALU Entity Declaration of a 32-bit ALU A B N Op Z entity ALU32 is port (A,B : in std_ulogic_vector(31 downto 0); C : out std_ulogic_vector(31 downto 0); Op : in std_ulogic_vector(5 downto 0); N,Z : out std_ulogic); end ALU32; 32-bit ALU A B N Op Z C 31 December 2018 Veton Këpuska

VHDL: Entity Entity Declarations can occur at multiple levels of abstraction, from a gate level to large systems. In fact it should be apparent that a design entity does not even have to represent digital hardware! Description of the interface is simply a specification of the input and output signals of the design entity. Once the interface to the digital component or circuit has been described, it is now necessary to describe its internal behavior. 31 December 2018 Veton Këpuska

VHDL: Architecture VHDL contsruct that enables specification of the functional description of the entity is the architecture construct. The syntax of the architecture construct is as the following: architecture half_adder_func of half_adder is -- declarations begin -- description of the function end half_adder_func 31 December 2018 Veton Këpuska

Summary of entity-architecture Construct Description of a design module takes the form of an entity-architecture pair. The architecture description is linked to correct entity description by providing the name of the corresponding entity. Description of the behavior provided in the architecture of the design module can take many forms depending on: The level of detail, Description of events, And the degree of concurrency. Next the core set of AHDL language constructs required to model the attributes of digital systems is described. 31 December 2018 Veton Këpuska

Concurrent Statements Operation of digital systems is inherently concurrent - Many components of a circuit can be simultaneously operating and concurrently driving distinct signals to new values. Within VHDL signals are assigned values using signal assignment statements. These statements specify a new value of a signal and the time at which the signal is to acquire this value. Multiple signal assignment statements are executed concurrently in simulated time and are referred to as concurrent signal assignment statements (CSAs). Several forms of CSAs will be described next. 31 December 2018 Veton Këpuska

Simple Concurrent Signal Assignement architecture half_adder_concurrent_behaviour of half_adder is begin sum <= (a xor b) after 5 ns; carry <= (a and b) after 5 ns; end half_adder_concurrent_behaviour; Name of the entity describing the interface of this design module is the name given of the architecture model “<=“ is a signal assignment operator 31 December 2018 Veton Këpuska

Operation of half_adder 31 December 2018 Veton Këpuska

Simple Concurrent Signal Assignement If an event (signal transition) occurs on a signal on the right hand side of a signal assignment statement: The expression is evaluated and New values for the output dependency of the output signals on the input signals is captured in the two statements and NOT in the textual order of the program. Both statements are executed concurrently with respect to simulated time to reflect the concurrency of corresponding operations in the physical system. Fundamental difference of VHDL programs and other conventional programming languages is that concurrency is a natural part of the systems described in VHDL. Complete half-adder description in VHDL is given next. 31 December 2018 Veton Këpuska

Simple Concurrent Signal Assignement Libraries can be thought of as repositories for frequently used design entities. The library clause identifies the library that we wish to access. library IEEE; use IEEE.std_logic_1164.all; entity half_adder is port (a,b: in std_ulogic; sum,carry: out std_ulogic); end half_adder; architecture half_adder_concurrent_behaviour of half_adder is begin sum <= (a xor b) after 5 ns; carry <= (a and b) after 5 ns; end half_adder_concurrent_behaviour; The name of the library typically indicates directory containing various design units that have been pre-compiled. A package is one such unit. A package may contain definitions of types, functions or procedures to be shared. The use clause determines which of the packages or other design units in a library will be used in a design. 31 December 2018 Veton Këpuska

VHDL Model of a full adder library IEEE; use IEEE.std_logic_1164.all; entity full_adder is port (in1,in2,c_in: in std_ulogic; sum,c_out: out std_ulogic); end half_adder; architecture full_adder_arch of full_adder is signal s1,s2,s3: std_ulogic; constant gate_delay: Time := 5 ns; begin L1: s1 <= (In1 xor In2) after gate_delay; L2: s2 <= (c_in and s1) after gate_delay; L3: s3 <= (In1 and In2) after gate_delay; L4: sum <= (s1 xor c_in) after gate_delay; L5: c_out <= (s2 or s3) after gate_delay; end full_adder_arch; Declarative Segment Body 31 December 2018 Veton Këpuska

Implementation of Signals Up to now we have seen the signals being declared in port declaration of an entity and in the body of an architecture construct. The form of signal declaration is: signal s1: std_ulogic := ‘0’; Or in general: identifier-list: type := expression; Optional expression if included defines initial value of the signal. If not included signal gets default initial value depending on it type. 31 December 2018 Veton Këpuska

Signal Value Assignment One form that was used so far to assign a value to the signal is: signal <= value expression after time expression; Right hand side of the of the signal assignment is referred to as waveform element. It describes an assignment to the signal and it is comprised of a: value expression Evaluates to a new value to be assigned to the signal, and time expression. Evaluates to the relative time at which the signal is to acquire this new value. With respect to current simulation time, this new time-value pair represents the future value of the signal and is referred to as a transaction. 31 December 2018 Veton Këpuska

Signal Value Assignment Evaluation of a single waveform element produces single transaction on a signal. VHDL supports multiple transactions with multiple waveform elements: s1 <= (a xor b) after 5 ns, (a or b) after 10 ns, (not a) after 15 ns; This is achieved by maintaining an ordered list of all of the current transactions pending on a signal. This list is referred to as driver of the signal. In general a whole waveform (time-value pairs) is assigned to the signal, rather then a single value at a particular time. 31 December 2018 Veton Këpuska

Signal Value Assignment Within the simulator the sequences of waveform elements are represented as a sequence of transactions on the driver of the signal. These transactions are referred to as the projected output waveform (since those events have not yet occurred in the simulation). VHDL provides specific rules for adding transactions to the projected waveform signal. Those rules aid in the cases when the simulation attempts to add transactions that conflict with the current projected waveform. 31 December 2018 Veton Këpuska

Resolved Signals The view of the signal up to now was the every signal had only one driver – that is there is only one assignment statement that is responsible for generating the waveform on that signal. In practice shared signals occur on buses and in circuits based on wired logic. Question arises as to how the signal value is determined when the signal has multiple values? In the VHDL this value is determined by a resolution function. 31 December 2018 Veton Këpuska

Resolved Signals Resolution function examines all of the drivers on a shared signal and determines the value to be assigned to the signal. A shared signal must be of a special type: resolved type. A resolved type has a resolution function associated with the type. In previous examples the types that were used were: std_ulogic and std_ulogic_vector Corresponding resolved types are: std_logic and std_logic_vector 31 December 2018 Veton Këpuska

Resolved Signals The distinction of the resolved and unresolved types has the following consequence: The correct value of the signal for resolved types is determined automatically by invoking the resolution function by default. Multiple drivers may be projecting multiple future values for a signal. Resolution function examines these drivers to return the correct value of the signal at the current time. For IEEE 1164 package the resolution function is essentially a lookup table. One source driving the signal to 1 Second source driving the same signal to 0 Resulting signal value will be X – unknown. Having multiple drivers on the same signal that is declared as unresolved type will result in an error. 31 December 2018 Veton Këpuska

Conditional Signal Assignment To model high-level circuits (multiplexers and decoders) it is required to have a richer set of constructs in the HDL language. Conditional signal assignment is one such construct. Any event on any one of the input signals (in0-in3) or any of the control signals (S0 or S1) may cause a change in the value of the output signal. Thus when ever an event takes place the concurrent signal assignment statement is executed and all four conditions may be checked. Order of expressions in right hand side is important. Multiplexer Example library IEEE; use IEEE.std_logic_1164.all; entity mux4 is port (in0,in1,in2,in3: in std_logic_vector (7 downto 0); S0,S1: in std_logic; Z: out std_logic_vector (7 downto 0) ); end mux4; architecture mux4_func of mux4 is begin Z <= in0 after 5 ns when S0=‘0’ and S1=‘0’ else in1 after 5 ns when S0=‘0’ and S1=‘1’ else in2 after 5 ns when S0=‘1’ and S1=‘0’ else in3 after 5 ns when S0=‘1’ and S1=‘1’ else ‘00000000’ after 5 ns; end mux4_func; 31 December 2018 Veton Këpuska

Selected Signal Assignment The value of the signal is determined by the value of a select expression. Example: Consider the operation of reading the value of a register from a register bank of eight registers. Depending on the value of the address (e.g., opcode) the contents of the appropriate register is selected. In the following VHLD code example of read-only register bank with two read ports is presented. 31 December 2018 Veton Këpuska

Selected Signal Assignment library IEEE; use IEEE.std_logic_1164.all; entity reg_bank is port (addr1,addr2: in std_logic_vector (2 downto 0); reg_out_1, reg_out_2: out std_logic_vector (31 downto 0) ); end reg_bank; architecture reg_bank_func of reg_bank is signal reg0,reg2,reg4,reg6: std_logic_vector (31 downto 0):= to_stdlogicvector(x“12345678”); signal reg1,reg3,reg5,reg7: std_logic_vector (31 downto 0):= to_stdlogicvector(x“abcdef00”); begin with addr1 select reg_out_1 <= reg0 after 5 ns when “000”, reg1 after 5 ns when “001”, reg2 after 5 ns when “010”, reg3 after 5 ns when “011”, reg3 after 5 ns when others; with addr2 select reg_out_2 <= reg0 after 5 ns when “000”, end reg_bank_func; 31 December 2018 Veton Këpuska

Constructing VHDL Models Using CSAs With Concurrent signal assignment statements we are now armed with the tool to construct VHDL models of interesting classes of digital systems. The following topic of this section will provide a prescription for constructing such VHDL models. 31 December 2018 Veton Këpuska

Summary Note that a VHDL model written using only concurrent signal assignment statements, the execution of a signal assignment statement is initiated: By the flow of data or signal values, and Not by the textual order of the statements. Based on the language features covered thus far, a model of a digital system will be comprised of entity-architecture pair. The entity portion declares the model’s interface; its input and output signals. The architecture model, in turn, will be comprised of some combination of simple, conditional, and selected signal assignments statements. The architecture model may also declare and use internal signals in addition to the input and output ports declared in the entity description. 31 December 2018 Veton Këpuska

Constructing VHDL Models Using CSAs The following description assumes that the we are writing a VHDL model of a gate level combinational circuit. The simple methodology comprises of two steps: Drawing of an annotated schematic, and Conversion to a VHDL description. 31 December 2018 Veton Këpuska

Constructing VHDL Models Using CSAs Schematic Construction of a Model Represent each component (e.g., gate) of the system to be modeled as a delay element. Draw a schematic interconnecting all of the delay elements. Uniquely label each component. Identify the input signals of the circuit as input ports. Identify the output signals of the circuit as output ports. All remaining signals are internal signals. Associate a type with each input, output , and internal signal, such as std_logic or std_logic_vector. Ensure that each input port, output port, and internal signal are labeled with a unique name. 31 December 2018 Veton Këpuska

Constructing VHDL Models Using CSAs Delay element model of a digital system D D D D D Input Ports Output Ports Internal Signals 31 December 2018 Veton Këpuska

A template for writing VHDL models using CSAs library library_name_1, library_name_2, …, library_name_n; use library-name_1.package-name.all; use library_name_2.package_name.all; … use library-name_n.package-name.all; entity entity_name is port (input signals: in type; output signals: out type); end entity_name; architecture artchitecture_name of entity_name is --declaration of internal signals signal internal_signal_1: type := initialization; signal internal_signal_2: type := initialization; signal internal_signal_m: type := initialization; begin -- specification of values of each signal as a function of other signals internal_signal_1 <= simple, conditional, or selected CSA; internal_signal_2 <= simple, conditional, or selected CSA; internal_signal_m <= simple, conditional, or selected CSA; output_signal_1 <= simple, conditional, or selected CSA; output_signal_2 <= simple, conditional, or selected CSA; output_signal_l <= simple, conditional, or selected CSA; end artchitecture_name; 31 December 2018 Veton Këpuska

Understanding Delays Important aspect of modeling is handling propagation delays. Accurate representation of the behavior of digital circuits requires accurate modeling of delays through the various components. In this section the delay modeling available in VHDL and how they are specified will be discussed. Note that those specifications can be incorporated easily into presented basic model template. 31 December 2018 Veton Këpuska

The Inertial Delay Model Real digital circuits have a certain amount of inertia. Thus it takes a finite amount of time and a certain amount of energy for the output of a gate to respond to a change on the input. This fact implies that that the change on the input has to persist for a certain period of time to ensure that the gate will respond with a change in the output. This propagation delay model is referred to as the inertial delay model and it is a default delay model for VHDL programs. 31 December 2018 Veton Këpuska

The Inertial Delay Model Any pulse with of a width of less than the propagation delay through the gate is will be rejected. In actual hardware the exact width of the pulse that is rejected is highly dependent upon the physical design and manufacturing process parameters. In general it can be difficult to determine accurately those characterize delay and thus specify rejection. Nevertheless VHDL uses the propagation delay through the component as the default pulse rejection width: signal <= reject time-expression inertial value-expression after time-expressions; sum <= reject 2 ns inertial (a xor b) after 5 ns; 31 December 2018 Veton Këpuska

The Transport Delay Model Real signals propagate through wires at a finite rate and experience delays that are proportional to the distance. However, wires have comparatively to switching devices less inertia. Wires will propagate any changes in signal values independent of the duration of the pulse width. Modern designs with increasingly small feature sizes the wire delays dominate. Designs thus seek to minimize wire length. Ability to model those delays, called transport delays, thus can be critical for some designs. In VHDL those delays can be specified by prefacing the waveform element with the keyword transport: sum <= transport (a xor b) after 5 ns; 31 December 2018 Veton Këpuska

An example of using transport delays library IEEE; use IEEE.std_logic_1164.all; entity half_adder is port (a, b: in std_logic; sum, carry: out std_logic); end half_adder; architecture half_adder_func of half_adder is begin s1 <= (a xor b) after 2 ns; s2 <= (a and b) after 2 ns; sum <= transport s1 after 4 ns; carry <= transport s2 after 4 ns; end half_adder_func; 31 December 2018 Veton Këpuska

Delta Delays What happens if inertial and transport delays are not specified? sum <= (a xor b); Delays can be ignored if they are not know, in which case the design can be only simulated for functional correctness without being concerned with the timing behavior. Correct ordering of the functional behavior is achieved within VHDL language by defining an infinitesimally small delay referred to as a delta delay. When delay is not specified each component is assigned a delay value equal to this Δ. Simulator uses this Δ to order the events appropriately. 31 December 2018 Veton Këpuska