Washington University CS/CoE 536 Reconfigurable System On Chip Design Lecture 9 : MP3 Working Draft Washington University Fall 2002 http://www.arl.wustl.edu/~lockwood/class/cs536/ John Lockwood Copyright 2002 Lockwood@arl.wustl.edu

Flow Pointer Initialization in SRAM Set up a head/tail pointer pair for all possible FlowIDs (16 bits) Every head/tail pointer must be unique. Head Pointer: x0 Tail Pointer: Packet Reads = 0 Packet Writes Head Pointer: x2 Tail Pointer: Packet Reads = 0 Packet Writes Head Pointer: x4 Tail Pointer: Packet Reads = 0 Packet Writes Head Pointer: x6 Tail Pointer: Packet Reads = 0 Packet Writes Head Pointer: xFFFE Tail Pointer: Packet Reads = 0 Packet Writes SRAM ADDR: FlowID & “00” SRAM ADDR: FlowID & “01” SRAM ADDR: FlowID & “10” Head Pointer: x1 Tail Pointer: Packet Reads = 0 Packet Writes Head Pointer: x3 Tail Pointer: Packet Reads = 0 Packet Writes Head Pointer: x5 Tail Pointer: Packet Reads = 0 Packet Writes Head Pointer: 7 Tail Pointer: Packet Reads = 0 Packet Writes Head Pointer: xFFFF Tail Pointer: Packet Reads = 0 Packet Writes SRAM ADDR: FlowID & “11”

Flow Pointer Initialization in SRAM Points to loaction in SDRAM Points to Location in SDRAM. It is intialized when reset_l=‘0’ to FlowID FlowID (16 bit) SRAM Address (18 bit) SRAM Data (32 bit) Queue Context Function Head Pointer 1 Packet Reads 2 Packet Writes 3 Tail Pointer 4 5 6 7 8

Others Issues with Flow Management .. Memory Contention Flow is empty when “Packet Writes” = “Packet Reads” Input: Flow must be added to output queue. Output: Flow must be removed from output queue.