FPGA Logic Synthesis using Quantified Boolean Satisfiability Andrew C. Ling, Deshanand P. Singh, and Stephen D. Brown University of Toronto, Canada PLB PLB PLB PLB LUT x0 … xn x0 … xn LUT PLB PLB PLB f ? g PLB PLB PLB 1) FPGA: Programmable Logic Structures and Routing 2) Problem: Determine if a given cone of logic can fit into a programmable circuit. LUT l0…lm x0…xn z0…zo (f ≡ g) f = output of cone g = output of programmable circuit l = configuration bits x = input signals z = intermediate wire signals E A E LUT ? LUT LUT LUT 4) Application 1: Technology mapping to Programmable Logic Blocks 5) Application 2: Resynthesis 3) Does there exist a configuration to a circuit, such that it can implement a given cone