Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt,

Slides:



Advertisements
Similar presentations
1 Fast Configurable-Cache Tuning with a Unified Second-Level Cache Ann Gordon-Ross and Frank Vahid* Department of Computer Science and Engineering University.
Advertisements

LEVERAGING ACCESS LOCALITY FOR THE EFFICIENT USE OF MULTIBIT ERROR-CORRECTING CODES IN L2 CACHE By Hongbin Sun, Nanning Zheng, and Tong Zhang Joseph Schneider.
1 A Self-Tuning Cache Architecture for Embedded Systems Chuanjun Zhang*, Frank Vahid**, and Roman Lysecky *Dept. of Electrical Engineering Dept. of Computer.
5th International Conference, HiPEAC 2010 MEMORY-AWARE APPLICATION MAPPING ON COARSE-GRAINED RECONFIGURABLE ARRAYS Yongjoo Kim, Jongeun Lee *, Aviral Shrivastava.
Copyright © 2008 UCI ACES Laboratory Kyoungwoo Lee, Minyoung Kim, Nikil Dutt, and Nalini Venkatasubramanian Error-Exploiting.
Copyright © 2006 UCI ACES Laboratory Kyoungwoo Lee 1, Aviral Shrivastava 2, Ilya Issenin 1, Nikil Dutt 1, and Nalini Venkatasubramanian.
Copyright © 2002 UCI ACES Laboratory A Design Space Exploration framework for rISA Design Ashok Halambi, Aviral Shrivastava,
Polynomial-Time Algorithms for Designing Dual-Voltage Energy Efficient Circuits Master’s Thesis Defense Mridula Allani Advisor : Dr. Vishwani D. Agrawal.
June 20 th 2004University of Utah1 Microarchitectural Techniques to Reduce Interconnect Power in Clustered Processors Karthik Ramani Naveen Muralimanohar.
Chia-Yen Hsieh Laboratory for Reliable Computing Microarchitecture-Level Power Management Iyer, A. Marculescu, D., Member, IEEE IEEE Transaction on VLSI.
Investigating the Effect of Voltage- Switching on Low-Energy Task Scheduling in Hard Real-Time Systems Paper review Presented by Chung-Fu Kao.
© ACES Labs, CECS, ICS, UCI. Energy Efficient Code Generation Using rISA * Aviral Shrivastava, Nikil Dutt
Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Systems Aviral Shrivastava 1 Nikil Dutt 1 Alex Nicolau 1 Sanghyun.
Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures (DIPES 08) Kyoungwoo Lee.
Compilation Techniques for Energy Reduction in Horizontally Partitioned Cache Architectures Aviral Shrivastava, Ilya Issenin, Nikil Dutt Center For Embedded.
CML CML Cache Vulnerability Equations for Protecting Data in Embedded Processor Caches from Soft Errors † Aviral Shrivastava, € Jongeun Lee, † Reiley Jeyapaul.
Compiler-in-the-Loop ADL-driven Early Architectural Exploration Aviral Shrivastava 1 Nikil Dutt 1 Alex Nicolau 1 Eugene Earlie 2 1 Center For Embedded.
ECE 510 Brendan Crowley Paper Review October 31, 2006.
Automatic Tuning of Two-Level Caches to Embedded Applications Ann Gordon-Ross and Frank Vahid* Department of Computer Science and Engineering University.
Lecture 0: Introduction. CMOS VLSI Design 4th Ed. 0: Introduction2 Introduction  Integrated circuits: many transistors on one chip.  Very Large Scale.
A Compiler-in-the-Loop (CIL) Framework to Explore Horizontally Partitioned Cache (HPC) Architectures Aviral Shrivastava*, Ilya Issenin, Nikil Dutt *Compiler.
Roza Ghamari Bogazici University.  Current trends in transistor size, voltage, and clock frequency, future microprocessors will become increasingly susceptible.
CML CSE 591: Advances in Reliable Computing Aviral Shrivastava.
Assuring Application-level Correctness Against Soft Errors Jason Cong and Karthik Gururaj.
Copyright © 2008 UCI ACES Laboratory Kyoungwoo Lee 1, Aviral Shrivastava 2, Nikil Dutt 1, and Nalini Venkatasubramanian 1.
An Efficient Algorithm for Dual-Voltage Design Without Need for Level-Conversion SSST 2012 Mridula Allani Intel Corporation, Austin, TX (Formerly.
Energy-Efficient Cache Design Using Variable-Strength Error-Correcting Codes Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu,
SiLab presentation on Reliable Computing Combinational Logic Soft Error Analysis and Protection Ali Ahmadi May 2008.
CML CML Compiler-Managed Protection of Register Files for Energy-Efficient Soft Error Reduction Jongeun Lee, Aviral Shrivastava* Compiler Microarchitecture.
CML CML Compiler Optimization to Reduce Soft Errors in Register Files Jongeun Lee, Aviral Shrivastava* Compiler Microarchitecture Lab Department of Computer.
Copyright © 2008 UCI ACES/DSM Laboratories 1 Nalini Venkatasubramanian 1 Kyoungwoo Lee,
Bypass Aware Instruction Scheduling for Register File Power Reduction Sanghyun Park, Aviral Shrivastava Nikil Dutt, Alex Nicolau Yunheung Paek Eugene Earlie.
LLMGuard: Compiler and Runtime Support for Memory Management on Limited Local Memory (LLM) Multi-Core Architectures Ke Bai and Aviral Shrivastava Compiler.
Critical Power Slope: Understanding the Runtime Effects of Frequency Scaling Akihiko Miyoshi †,Charles Lefurgy ‡, Eric Van Hensbergen ‡, Ram Rajamony ‡,
Optimisation of Pipelined MPSoCs Using Integer Linear Programming Embedded Systems Laboratory Haris Javaid Research Associate.
Eduardo L. Rhod, Álisson Michels, Carlos A. L. Lisbôa, Luigi Carro ETS 2006 Fault Tolerance Against Multiple SEUs using Memory-Based Circuits to Improve.
Physically Aware HW/SW Partitioning for Reconfigurable Architectures with Partial Dynamic Reconfiguration Sudarshan Banarjee, Elaheh Bozorgzadeh, Nikil.
EnerJ: Approximate Data Types for Safe and General Low-Power Computation (PLDI’2011) Adrian Sampson, Werner Dietl, Emily Fortuna Danushen Gnanapragasam,
A Protocol for Tracking Mobile Targets using Sensor Networks H. Yang and B. Sikdar Department of Electrical, Computer and Systems Engineering Rensselaer.
A Multi-Mode Selectable DC-DC Converter for Ultralow Power Circuits Ernie Bowden Doug Sorenson.
Spring 2008 CSE 591 Compilers for Embedded Systems Aviral Shrivastava Department of Computer Science and Engineering Arizona State University.
Gill 1 MAPLD 2005/234 Analysis and Reduction Soft Delay Errors in CMOS Circuits Balkaran Gill, Chris Papachristou, and Francis Wolff Department of Electrical.
A Novel, Highly SEU Tolerant Digital Circuit Design Approach By: Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M.
Multiplication Find the missing value x __ = 32.
Introduction to CMOS VLSI Design Lecture 0: Introduction.
Logic Families.
Kyoungwoo Lee1, Aviral Shrivastava2, Ilya Issenin1,
Problem and Motivation
Reducing Code Management Overhead in Software-Managed Multicores
SE-Aware HPC Extension : Selective Data Protection for reducing failures due to soft errors 7/20/2006 Kyoungwoo Lee.
Multiplication table. x
June 2007 An Experimental Study on Energy Consumption of Video Encryption for Mobile Handheld Devices Kyoungwoo Lee, Nikil Dutt, Nalini Venkatasubramanian.
Improving Program Efficiency by Packing Instructions Into Registers
Splitting Functions in Code Management on Scratchpad Memories
Main Memory Database Systems
Gabor Madl Ph.D. Candidate, UC Irvine Advisor: Nikil Dutt
Design Space Exploration
EE201C Modeling of VLSI Circuits and Systems Final Project
Mitigating the Impact of Hardware Defects on Multimedia Applications – A Cross-Layer Approach 1Kyoungwoo Lee, 2Aviral Shrivastava, 1Minyoung Kim, 1Nikil.
EE201C Modeling of VLSI Circuits and Systems Final Project
Ann Gordon-Ross and Frank Vahid*
Dual Mode Logic An approach for high speed and energy efficient design
Closure Representations in Higher-Order Programming Languages
Design of a ‘Single Event Effect’ Mitigation Technique for Reconfigurable Architectures SAJID BALOCH Prof. Dr. T. Arslan1,2 Dr.Adrian Stoica3.
Die Stacking (3D) Microarchitecture -- from Intel Corporation
Kyoungwoo Lee, Nikil Dutt, and Nalini Venkatasubramanian
Kyoungwoo Lee (final defense)
Kyoungwoo Lee, Minyoung Kim, Nikil Dutt, and Nalini Venkatasubramanian
Realizing Closed-loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges Islam S. Badreldin*, Ann Gordon-Ross*,
Automatic Tuning of Two-Level Caches to Embedded Applications
Presentation transcript:

Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt, and Nalini Venkatasubramanian IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEM Dohwan Kim

Table of contents Soft error Failure noncritical (FNC) and failure critical (FC) Partially protected cache (PPC) Design space exploration (DSE) algorithm Conclusion

Soft error A high-energy radiation particle may strike the diffusion region of a complementary metal-oxide- semiconductor transistor. This phenomenon changes the logic state of a transistor. Soft error is not repeatable error.

FNC and FC In multimedia applications Failure noncritical (FNC) data: the image data or audio data Failure critical (FC) data: the loop variable or the stack pointer

FNC and FC A cache miss, generally, is when something is looked up in the cache and is not found.

PPC Partially protected cache architecture Unprotected cache -> FNC Protected cache -> FC Increased transistor size, increased supply voltage, SEC- DED, etc

PPC It is important to choose the best configuration of a PPC to satisfy multiple design constraints such as the failure rate, power, and performance. Size of protected cache ↑ -> failure rate ↑ cache miss rate ↓ Set associativities ↑ -> performance ↑ energy consumption ↑

DSE algorithm BFExplore algorithm S: a set of sizes of the protected cache A: a set of set-associativity from 1-way to 32-way Constraints: runtime and energy consumption

DSE algorithm BFExplore algorithm

DSE algorithm BRExplore algorithm S: a set of sizes of the protected cache A: a set of set-associativity from 1-way to 32-way Constraints: failure rate and energy consumption

DSE algorithm BRExplore algorithm

Conclusion They propose PPC which can mitigate failures caused by soft errors in multimedia embedded applications. They also propose heuristic algorithms, BFExplore and BRExplore, to efficiently find the best configuration for proposed PPC architectures.