V.Navaneethakrishnan Dept. of ECE, CCET VLSI Lay-out Design V.Navaneethakrishnan Dept. of ECE, CCET

VLSI DESIGN Custom Design Semi-Custom Design Standard Cell Gate Array Programmable Devices PLA/PAL CPLD FPGA SOC

Fabrication Process begins with silicon wafers basically formed out of sand

A series of process steps, including epitaxial growth, dielectric and metal layer depositions, oxidation, diffusion, ion implantation and several steps of Lithography …. then follow

……………………………………… ……………………………………… ……………………………………… ……………………………………… 1. 2. 3. Substrate p Thick oxide (1m) ……………………………………… ……………………………………… p Photoresist ……………………………………… ……………………………………… p

……………………………………… ……………………………………… ……………………………………… 4. 5. UV light Mask p Window in oxide ……………………………………… ……………………………………… p

……………………………………… ……………………………………… ……………………………………… ……………………………………… ………… 6. 7. ……………………………………… Patterned Poly. (1-2 m) On thin oxide ( 800-1000A0 ) ……………………………………… ……………………………………… ……………………………………… p n+ diffusion (1 m deep) ………… ………… ……………………………………… ……………………………………… …… …… p

…… ………… …… ………… …… …… ……. ………… ………… ………… ………… …… ………… …… ………… 8. …… ………… …… ………… …… …… ……. ………… ………… ………… ………… Contact holes (cuts) …… ………… …… ………… ……………………………………… ……………………………………… p 9. …… ………… …… ………… …… …… ……. Patterned Metallization (aluminum 1 m) ………… ………… ………… ………… …… ………… …… ………… ……………………………………… ……………………………………… p

Drain-to-source current Ids versus voltage Vds relationship nMOS Transistor structure: Gate Drain W D Source L Charge induced in channel (Qc) Electron transit time() Ids = Isd = (1) Length of channel (L) Velocity(v) sd = First, transit time:

Pass transistor And gate : VDD X A B C X = A.B.C (Logic 1 = VDD – Vt ) nMOS inverter : Vin Vout VDD GND

nMOS depletion mode transistor pull-up and transfer characteristic Vout Vt Vin Vout VDD GND No current Current flows Non-zero output Vin

4. Complementary transistor pull-up (CMOS) : No current flow either for logical 0 or for logical 1 inputs. Full logical 1 and 0 levels are presented at the output. For devices of similar dimensions the p-channel is slower than the n-channel device. Vout Vtn Vtp VDD VDD p (ii) Transfer characteristic p on n off Vout both on Vin n p off n on Vin VSS VSS VDD (i) Circuit Regions Current (between ralls) 1 2 3 4 5 (iii) CMOS inverter Current versus Vin Vin

An improved BiMOS inverter using MOS transistors for base current discharge VDD T4 T2 Vin T5 Vout T3 T1 CL T6 GND VSS

… … ……………………………………… …… ………… …… 1. 2. SiO2 p-well (4-5 m) Thin oxide Polysilicon 2. …… ………… …… Thin oxide and polysilicon p n

…… ………… …… …… ………… …… 3. 4. P+ mask (positive) P+ mask (negative) p-diffusion P+ mask (positive) 3. …… ………… …… p n P+ mask (negative) n-diffusion 4. …… ………… …… p n

CMOS p-well inverter showing VDD and VSS substrate connections Polysilicon Oxide n-diffusion P-diffusion Vin Vout VDD VSS p n CMOS p-well inverter showing VDD and VSS substrate connections

CMOS n-well inverter showing VDD and VSS substrate connections Polysilicon Oxide n-diffusion P-diffusion Vin Vout VDD VSS n p CMOS n-well inverter showing VDD and VSS substrate connections

( A logical extension of the p-well and n-well) Polysilicon Oxide n-diffusion P-diffusion Vin Vout VDD VSS Epitaxial layer n well p well n substrate Twin-tub structure ( A logical extension of the p-well and n-well)

Encodings for a simple single metal nMOS process Stick diagram Encodings for a simple single metal nMOS process COLOR STICK ENCODING LAYERS MASK LAYOUT ENCODING CIF LAYER MONOCROME GREEN RED BLUE BLACK GRAY n-diffusion n+active Thniox Polysilicon Metal 1 Contact cut Overglass NOT APPLICABLE nMOS ONLY YELLOW Implant Buried contact nMOS ONLY BROWN ND NP NM NC NG NI NB

Lamda-based design rules Minimum separation Minimum width n-diffusion p-diffusion 2 3 2 1 1 2 2 Metal 1 Minimum width 2 3 3 Metal 2 3 4 4 4

Transistor design rules nMOS (enhancement) pMOS (enhancement) nMOS (depletion) Separation from contact cut to transistor Implant for an nMOS depletion mode transistor to extend 2 minimum beyond channel in all directions 2 minimum Separation from implant to another transistor 2 minimum

Stick diagram and layout for nMOS shift register cell Lamba VDD 25 20 4:1 15 2:1 10 GND 5 2 2 2 5 10 15 20 25 Lamba

Stick diagram and layout for nMOS shift register cell Lamba VDD 25 20 4:1 15 2:1 10 GND 5 2 2 2 5 10 15 20 25 Lamba

Two way selector with enable X O/P Y A A’ E X O/P Y A A’ E

Thank You !!!