COMBINATIONAL LOGIC DESIGN EMT 251

CMOS Characteristics (Refresh)

CMOS Transistors (N-type)

CMOS Transistors (P-type)

Reality NMOS pulling to GND (Pull Down Network) PMOS pulling to Vdd (Pull Up Network) * the output is pull up to Vdd or Pull down to GND

Combinational vs Sequential

Combinational vs Sequential Logic a type of logic circuit whose output is a pure function of the present input only. output depends not only on the present input but also on the history of the input. Output = f ( In ) Output = f ( In, Previous In )

Combinational vs Sequential Logic CMOS Schematic Combinational Logic (Static) Sequential Logic (Dynamic) Complementary CMOS Transmission Gates Pass Transistor Pseudo-NMOS Domino Logic NORA Logic

Static Complementary CMOS

Static Complementary CMOS At every point in time (except during the switching transients) each gate output is connected to either V DD or ss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

Static Complementary CMOS VDD In1 PMOS only In2 PUN … InN F(In1,In2,…InN) In1 In2 PDN … NMOS only InN PUN and PDN are dual logic networks

NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high

PMOS Transistors in Series/Parallel Connection

Inverter Gate

NAND Gate

NOR Gate

Complex CMOS Gate B C A D OUT = D + A • (B + C) A D B C NMOS devices in series implements the AND function and parallel device implements the or function. Starts with PDN PUN is complement of PUN. B C A D OUT = D + A • (B + C) A D B C

Constructing a Complex Gate