Subcircuits subcircuits Each consists of one or more transistors. They are not used by themselves.

Subcircuits Switches Diodes/active resistors Current mirrors Current sources/current sinks Current/voltage references Band gap references

MOS switches Ideal Switch MOS transistor as a switch

Non-ideal switch: ron: On resistance roff: Off resistance VOS: On offset Ioff: Off offset IA and IB: leakage to gnd CA, CB: caps to gnd CAC, CBC: caps between control and switch terminals

Simple approximation On operation: VG >> VS or VD, VDS small, triode RON A B Off operation: VGS < VT , cutoff A B Very good off-char

Von=VG-max{VA, VB} Operation as a switch

For better Ron, use large W/L and use large Vgs - VT

Ron details with a log scale

Observations: RON depends on W, L, VG, VT, VDS, etc RON is nonlinear (depending on signal) Want: RON small and constant Strategies: Use large W and small L to reduce RON Use large VGS to reduce the effect of signal dependency Use bootstrapping to increase VGS beyond VDD–VSS Use constant VGS Use constant VB so as to have fixed VT

Effects of switch non-idealities Finite ON Resistance Non-zero charging and discharging time Limit settling Limits conversion rate Actually: takes time Ideally: instantaneous charging

Signal level dependence of RON Different settling behavior at different signal levels Introduces nonlinearity Generate higher order harmonics Vin: pure sine wave VC1: has harmonic distortions

Finite OFF Current Leakage of a held voltage Coupling through the switch Accumulates with time

Clock Feed through

EXAMPLE - Switched Capacitor Integrator (slow clock edge) Assume:

At t2: At t3: Once M2 turns on at t3, all charge on C1 is transferred to C2

Between t3 and t4 additional charge is transferred to C1 from the channel capacitance of M2. At t4: Ideal transfer: Total error:

Charge injection When switch is turned off suddenly, charges trapped in the channel is injected to both D and S side equally. The amount of trapped charges depends on the slope of VG

=U slow regime: L Hold value error on CL:

In the fast edge regime: Hold voltage error on CL: Study the example in the book

Dummy transistor to cancel clock feed through Complete cancellation is difficult. Requires a complementary clock.

Use CMOS switches Advantages - 1.) Larger dynamic range. 2.) Lower ON resistance. Disadvantages - 1.) Requires complementary clock. 2.) Requires more area.

Thus, the NMOS is in slow transition and the PMOS is in fast transition regimes.

Voltage doubler for gate overdrive

Constant VGS Bootstrapping f=0 f=1 VG=0 VDD VGS~VDD

Cp: total parasitic capacitance connected to top plate of C3. When f=1: Cp: total parasitic capacitance connected to top plate of C3. A.M. Abo and P.R. Gray, “A 1.5V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter, IEEE J. of Solid-State Circuits, Vol. 34, No. 5, May 1999, pp. 599-605.

Summary on Switches To reduce RON To reduce clock feed through Use large W and small L Use CMOS instead of NMOS or PMOS Use large |VGS| To reduce clock feed through Use cascode Use dummy transistor To reduce charge injection Use dummy Use slow clock edge Use complementary clock on switch and dummy To improve linearity Use vin-independent VGS Use vin-independent VBS (PMOS switch)

Diodes And Active Resistors Simple diode connection Voltage divider Extending the dynamic range Parallel MOSFET resistor Differential resistor Single MOSFET Double MOSFET

Diode Connection VDS = VGS  Always in saturation If v > VT, i > 0 else i = 0 diode i v VT

Generally, gm ≈ 10 gmbs ≈ 100 gds If VBS=0,

Voltage Division, gm in saturation Equating iD1 to iD2 results in: VDS1 +VDS2 = VDD - VSS Can use different W/L ratio to achieve desired voltage division Use less power than resistive divider

Active vs passive resistors Suppose Vo=(VDD+VSS)/2 =2 gm1=gm2=bVEB=10*0.2=2 m Ro=1/4m = 250 ohm Ro Io=b/2 *(VEB)2=0.2mA =0 To achieve the same Ro, need two 500 ohm resistors. Io=2/(2*500)=2mA, 10 times Ro Consumes 10 times more power

Gds in saturation For the same small signal resistance and same current, MOSFET requires much less voltage. For the same R and same V, MOSFET delivers much more current.

Triode transistor as resistor Voltage controlled resistor. VAB should be very small. R change with VAB,  nonlinear

Current sources / sinks V Current source I I Current sink V I V

Non-ideal current sources / sinks

Two critical figures of merit How flat the operating portion is How small the non-operating region is rout and vmin For the simple sink on prev slide:

Increasing Rout

Cascode Current Sink

Reduction of VMIN Very flat Too large rout ≈ rds1*gm2rds2 is large which is good But vmin = vT +2VON needs to be reduced

Both just saturating But the 2 IREFs must be the same. How?

M6 is ¼ the size, it requires 2 times over drive, or 2 times VEB, or 2 time VON Very flat VMIN is much smaller

Alternative method M5 is ¼ the size Again, the 2 IREFs must be the same.

VON ≈ 0.6V Larger W/L ratio can significantly reduce VON

Matching Improved by Adding M3 Why is it better now?

Regulated Cascode Current Sink Near triode, VDS3↓, iout ↓, VGS4 ↓, VD4 or VG5 ↑, Iout ↑.

HW: As we pointed out, the circuit on the previous page suffers from a large Vmin. Modify the circuit to reduce Vmin without affecting rout. Once you do that, VDS for M1 and M2 are no longer matched. Introduce another modification so that the VDSs are matched.

=

Current Mirrors/Current Amplifiers

Simple Current Mirrors Assuming square law model:

Simplest example

Use of transistor W to control current gains

If mCox and VT matched: If vDS matched: Current gain or mirror gain is controlled by geometric ratio, which can be made quite accurate

Sources of Errors Mismatches in W/L ratios Mismatches in mCox Use large W, L PLI Mismatches in mCox Large area, common centroid, higher order gradient cancellation Mismatches in vDS Make vDS the same Mismatches in VT Large area, cancel gradient, same VBS

l effect:

VT mismatch effect:

Sensitivity A systematic way of computing errors. r =

Note: common mode errors do not contribute to matching errors, only differential errors do Therefore, can take:

Strategies to reduce errors Matching layout PLI, common centroid, symmetry, gradient,… Increased area Matching operating conditions VD, VS, VB, current densities, …  use cascoding to fix VDS Reduce the sensitivies Use large VGS-VT Make equivalent l small, make go small,  use cascoding to reduce go

Straightforward layout to achieve mirror ratio of 4: Matching accuracy not good.

Will have better matching But: only approximate common centroid no pli S G G S G G S G G S G G S G G S Will have better matching But: only approximate common centroid no pli can be more compact HW: suggest a better layout for ratio of 4.

Cascoding M1 and M2 are the mirror pair that determines io. VDS1 and VDS2 matched go is small

Small signal model

Wilson Current Mirror go is small VDS1 and VDS2 not matched

Small signal circuit

Computation of rout

Improved Wilson Current Mirror

HW: In the improved Wilson current mirror: What is rout? What is Vmin? The resistance from D2 to GND is 1/gm which is small. Why not connect G2 to a constant bias to increase that impedance?

SPICE simulation

Regulated Cascode Current Mirror Same as the regulated cascoded curren sink VDS2 is very stable with respect to vo, but not insensitive to Ireg change, not necessarily better matching

Implementation of IREG using a simple current mirror