A High Performance SoC: PkunityTM Chen Jie Peking University Microprocessor R&D Center

Contents PkUnity SoC Introduction PkUnity SoC Low Power Design

Introduction To introduce our lab history and our works, from 97 we began to develop processor, now we have UniCore Processor family and Pkunity SoC family, and many other relative chip products.

PKUnity-3 Architecture

UniCore fix-point processor UniCore Frequency: 600MHz 32-bit harvard-architecture RISC CPU UniCore32 instruction set compatible Add conditional mov & BLX instructions 8-stage instruction pipeline Dynamic prediction policy: G-share Pipelined I&D Cache Two-level TLB

Performance Evaluation Unicore-II CPI increase 10％-15% G-share prediction, pipelined cache, two-level TLB reduce the increasing of CPI caused by deep pipeline UniCore-II MIPS increase 70%- 80 % Performance improvement come from improvement of micro-architecture and technology

SoC Design Platform To build : In PkUnity-3: a chip-based infrastructure a integrated develop environment a design and verification flow In PkUnity-3: CPU configurable BUS configurable Interrupt system configurable DMA configurable Frequency configurable Power management

HW/SW Co-verification Coverage-oriented VERA verification flow SystemC-based HW/SW Co-verification methodology FPGA prototype

Contents PkUnity SoC Introduction PkUnity SoC Low Power Design Power research status PkUnity low power design and power estimation Future work

Power : New Challenge Power is a dramatic issue for SoCs with billions of transistors Power has to be reduced for portable devices that require a dramatic increase of computation power Deep submicron technologies (90 and 65 nm) will present a dramatic increase of leakage power Power still too high for most SoCs SoC Architectures, HW/SW, multiprocessor, multiple memories, are not well supported by CAD tools Reconfigurability and Flexibility compromises low-power Leakage and very low Vdd are dramatic problems

low power design technology and research topics LP Research Condition Technology Feature size shrink, low dielectric constant material, SOI technology Circuit Design low power standard cell library Gate Design low power logic chain: gated clock, gated Vdd RTL reduce switching activity: gated clock, state machine & glitch optimization Micro-arch Parallel, Pipeline, Pre-computing Instruction Good task partition between HW/SW, design low power instruction set Compiler Saving power while improve performance, Memory organization OS Dynamic voltage scaling, I/O devices, Power and energy analysis of OS Application Task partition, Algorithm optimization low power design technology and research topics

Power Estimation Research Power Estimation Hierarchy System Algorithm Register Transfer Logic Circuit Analysis Precision Analysis Speed High level architectural model SimplePower simulation vs. analysis Wattch CACTI simulation with timing info extract circuit parameters adding technology info gate level simulation PrimePower PowerCompiler analysis with extractive parameter HSPICE

Power of Pkunity Embedded Processor: High Performance vs. Low Power Three methods to reduce chip power: Close unused module Frequency scaling Close Pll Pkunity-3 object: CPU <800mW@1.8V/600MHz SoC <2000mW@1.8V/600MHz

Power Estimation

Power optimization Close unused module through gated clock Reduce chip power through scaling among multiple run mode Run Idle Sleep Change chip frequency through dynamic PLL configuration Input vector control in Execution components

Low power design and estimation flow Work Flow Low power design and estimation flow

Future Work Low Power Design Memory architecture (cache, TLB, register file) Clock system ( Syn vs. Asyn ) Bus system Instruction set selection Voltage and frequency scaling Compiler optimization Task movement Power Estimation To pre-analyze arch & micro-arch design through fast and accurate Architectural level power simulator To build a full-chip power simulator Power simulator parameter reconfigurable To build accurate leakage power estimation model Specific component power model

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