7-PMT cluster + Slow control + DRS4 readout system ver.3 by Dragon Backplane Trigger(L0+L1) +DRS4 readout preamp Slow- Control CW-HV 14 cm 7 PMTs 48cm

Improvement of DRS4 readout board Ver.2 Mar. 2011 Main-Amp Mezzanines were removed. Devices are mounted directly on the DRS4 readout board to facilitate attachment of a cooling device FPGA: Virtex-4 to Spartan-6 for lower cost (–450 €) 8 months Compact (–12cm) Ver.3 Nov.2011 13.6 cm ~31cm M.Aono, Y.Awane, Y.Konno (Kyoto U.), M.Ikeno, T.Uchida, M.Tanaka(KEK), T.Nakamori(Waseda U.)

Performance of DRS4 readout board ver.3 100ns FPGA coding and signal check are in progress. 7-PMT cluster signals are digitized and then transmitted via GbitE.

Main Amplifier + DRS4 readout system –dynamic range– DRS4 input (maximum) High Gain Low Gain 1 p.e. ~ 1.4mV Dynamic Range for PMT(gain 4x104) + Preamp(gain=10) High Gain: ~60 p.e. Low Gain: 3000 p.e. measured with ver.3 board

Main Amplifier + DRS4 readout system –Bandwidth– 300MHz -3dB High Gain Low Gain measured with ver.3 board DRS4 4ch cascade limits the bandwidth < 300MHz The difference of bandwidths between high and low gains is due to the difference of the main-amplifiers connected to the inputs of DRS4. ・faster amp? ・additional buffer? – to be implemented in the next version

DRS4 evaluation board v3 made by PSI w/o cascading 2ch cascading －３ｄB －３ｄB ５００MHz ６５０MHz （７５０MHｚ in the data sheet）

Main Amplifier mezzanine –bandwidth– Preamp HIGH GAIN(×9) PMT 1 unit / card ×2 ×4.5 5cm ADA4927 TRIGGER(×4) 1.8cm PMT gain=4x104 ×2 ADA4950 Attenuator ×1/4 LOW GAIN(×1/4) ×1 400MHz ADA4950 100M 1G Low Gain -3dB High Gain Normalized Gain [dB] Trigger The bandwidth of (Preamp + Main-amp + DRS4) will be measured with the DRS4 readout board ver.3. R.Hagiwara, S.Gunji (Yamagata U.), M.Ikeno, M.Tanaka(KEK)

DRS4 readout board ver.3 with trigger boards Digital L0 (Dragon) L1 (DESY) x3 Red number shows the number of boards in Japan Backplane (Dragon) Analog L0-sum (IFAE) x1 (Additional two boards are to be sent from Spain this month) L1 distribution(CIEMAT)x3 L0 fanout (UCM) x3 L1 decision (UCM) x3 Analog L0-majority (IFAE)x1 (Additional two boards are to be sent from Spain this month)

Status of test of analog trigger boards R. Hagiwara, S. Gunji (Yamagata Univ.), Y.Awane, H. Kubo (Kyoto Univ.) T. Nakamori (Waseda Univ.), and CTA-Japan-ELEC J. Boix (IFAE), L.A.Tejedor (GAE)

Integration test – analog trigger(1) Pulser x1 + Readout board ver2 (Dragon) + Analog L0 majority + Backplane (Dragon) + Fanout L0_majority_in 600mV PMT input 60mV L0_majority_out NIM Pocket Pulser L0 , L1 mezzanine L0_sum_in BP , Fanout 600mV Readout board 150mV L0_sum_out Pulser Main-amp L0 BP R.Hagiwara, S.Gunji(Yamagata U.), T.Nakamori(Waseda U.)

Elapsed time from the input to the output . (L0 trigger) Majority trigger Sum trigger Ch Delay[nsec] 6.776 1 6.909 2 6.802 3 6.837 4 6.915 5 6.825 6 6.648 Ch Delay[nsec] 6.112 1 6.088 2 6.124 3 6.110 4 6.137 5 6.150 6 6.165 L0_sum_in L0_sum_out Elapsed time Elapsed time

Summary Majority Sum Power Consumption [mW/ch] （ Measured by Spain group） 190 360 average elapsed time from the input to the output (Measured by Yamagata Univ.) 6.816 nsec 6.127 nsec maximum value of the 7 chs’ deviation for the elapsed time (Measured by Yamagata Univ.) 0.267 nsec 0.077 nsec same timing same timing These right figures correspond to the sum of signals for two channels. The upper figures correspond to the sum signal in the case that the two signals are imultaneously input . The lower figures correspond to the sum signal in the case that one signal is input 5 nsec later than the other signal. With 5 nsec delay, the pulse height of the signal for two photons become a half. As the pulse width of real signal is about 3 nsec, the influence due to the timing difference will be more critical. sum for 2 signals sum for 2 signals 10nsec delay of 5 nsec delay of 5nsec sum for 2 signals sum for 2 signals

Integration test – analog trigger(2) Pulser DRS board v2 L0 Fan-out BP Test pulse L0 majority L1 decision L0_fanout_in L0_fanout L1_signal L1_signal L0_fanout_out L0_fanout

Elapsed time from the input to the output . (L0 fanout) Ch Delay[nsec] 1 6.152 2 6.512 3 6.883 5 6.593 6 6.511 7 3.474 L0_fanout_in L0_fanout_out Elapsed time L0 Fan-out BP point 1 The delay time indicates the elapsed time from the point 1 to the point 2. point 2

Elapsed time from the input to the output is 4.246 nsec . (L1 decision) In some measurements, the reflection of the pulse was observed. L1_decision_in L1_decision_out Elapsed time

Status of test of digital trigger boards There is no further result after the Madrid meeting because a graduate student is in the job hunt and seldom comes to the university.

Test of PACTA developed by D.Gascon et al Preamp. in the current PMT cluster: Mini-Circuits LEE-39+ Gain= ~10, Power = +5V x 35mA = 175 mW (typ) PACTAv1.1 has less power consumption and higher gain. We started measurement of the performance of a new PACTA chip. 1p.e. spectrum with PACTA + main-amp (Dragon) + DRS4 evaluation board (PSI) PACTAv1.1 HV:850V @PMT Gain =5.0 x 104 Single-end output is used. (Test of diff. outputs is in progress.) Schematic was designed by Gascon et al. PCB was made by Dragon collab. K.Umehara, H.Katagiri (Ibaraki U,), R.Hagiwara, S.Gunji (Yamagata U.), M.Teshima, H.Ohoka (ICRR)

Development of a new PACTA evaluation board A test board equipped with a new PACTAv1.2 chip is being designed by Barcelona Univ with Dragon Collab. for evaluation of performance. Power consumption: 2 diff. outputs:120-150mW; 2 single-end outputs:80-120 mW Schematics PCB layout The schematics and PCB layout are fixed. The test board is being manufactured and will be sent from Barcelona to Japan around at the beginning of March for doing some tests.

Measurement of Temperature dependence of DRS4 chip Temperature in the camera will be controlled with an accuracy of ~ 1 degree by a cooling system using heat pipes. But there can be some temperature gradient. Uncertainty of the chip performance for temperature must be evaluated. Experimental Setup PC DRS4 Evaluation Board pulser Thermostat camber pulser : KEITHLEY 50MHz Arbitrary Waveform /Function Generator 3390 Temperature of the evaluation board was controlled from ~10℃ to 50℃.

Temperature dependence cell by cell Timing jitter (nsec/degree) Offset (mV/degree) Gain (/degree) N(cell) N(cell) N(cell) voltage/temperature(mV/degree) gain/temperature(/degree) timing-(cell No.) * (1/f_samp) /temperature(nsec/degree) Mean : -0.12 RMS : 0.02 Mean : -1.95e-04 RMS : 0.15e-04 Mean : -0.0023 RMS : 0.0012 Variation of temperature characteristics among cells is small. Temperature dependences are so small that impact on signal estimation is negligible compared with other uncertainties. DRS4 chips are stable for temperature that calibration for temperature is not strongly required.

Future plan Test of Analog/Digital trigger (before the Camera Review) PMT signal Three clusters A DRS4 readout board is to be shipped to CIEMAT this week Development of the next version (=ver.4) of DRS4 readout board Change of the pin assignment of the connector between the DRS4 board and the PMT-cluster because Gascon PACTA chip has low and high gain outputs. (c.f. a output from commercial chip in ver.3) Improve the bandwidth by faster main-amp. ?? Schedule (unfixed..) Design fix before Jul Board delivery in Sep.