MicroBaby Datapath.

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Presentation transcript:

MicroBaby Datapath

Copyright 2015 - Joanne DeGroat, ECE, OSU MB Datapth The MicroBaby Datapath – the main part of the processor – composed of : The MB ALU An accumulator A B input, which also has a latch register to hold the value when the bus returns to high impedance, Z Output driver to drive the bidirectional data bus. The objective is to implement this in VHDL, verify the implementation, and then synthesize it in Quartis. Copyright 2015 - Joanne DeGroat, ECE, OSU

Copyright 2015 - Joanne DeGroat, ECE, OSU The MB datapath The datapath has the following structure Copyright 2015 - Joanne DeGroat, ECE, OSU

Copyright 2015 - Joanne DeGroat, ECE, OSU Datapath components The MB ALU An 8-bit register for the accumulator Ldac – load the accumulator with the value on its input A 2-to-1x8 mux before the accumulator Aal control signal selects between the ALU result and the databus input A 2-to-1x8 mux before the Blatch Bbu selects between a fixed input of “00000000” and the databus input An 8-bit register to hold the Binput to the accumulator This is needed to prevent connection of the Binput to the ALU directly to the databus which goes back to high impedance, Z A BusDriver Allows the contents of the accumulator to be driven onto the bus Copyright 2015 - Joanne DeGroat, ECE, OSU

Control signal summary Aal – Accumulator input selection Bbu – B input select Ldac – Load the accumulator (positive edge) Dracc – Drive the accumulator value onto the databus Bmuxlatch – Load the Blatch with data F(3 dt 0) – the function code (ALU) AddSub – add or subtract (ALU) Cin – the Carry input (ALU) Arlo – arithmetic or logic operation (ALU) Csel – the carry input mux to the adder of the ALU DataBus – the databus which runs on a bus cycle Cout – the ALU carry flag N – the ALU N flag Z – the ALU Z flag Copyright 2015 - Joanne DeGroat, ECE, OSU

Copyright 2015 - Joanne DeGroat, ECE, OSU The last step You will be modeling each of these components, HDL simulating it, and then synthesizing it using Quartis. A model of components will be provided along with an HDL testbench. Copyright 2015 - Joanne DeGroat, ECE, OSU

Copyright 2015 - Joanne DeGroat, ECE, OSU

Copyright 2015 - Joanne DeGroat, ECE, OSU

Copyright 2015 - Joanne DeGroat, ECE, OSU

Copyright 2015 - Joanne DeGroat, ECE, OSU