As lithography continues to shrink, the problem of driving

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Presentation transcript:

As lithography continues to shrink, the problem of driving Min L NMOS transistor As lithography continues to shrink, the problem of driving Large currents increases.

For Current Drivers Large Cascaded Transistors are needed Such circuits require large amounts of chip area and have slow Signal transition time. Example: Driving a milliamp With 50 microamp CMOS Area=30 transistors Delay=11 gates Current= 1 mA 50 135 369 1000 Staging Delay The number of stages necessary and minimum delay in driving a current Il, when the minimum transistor size has a current drive Im can be computed from the capacitance of the gate of the minimum transistor size Cm. If a single stage is used, the delay will be proportional to: Im[(Il/ Im)(Cm)]= Il Cm as compared to the minimum delay proportional to Im Cm. If a number of stages N is used, and the loading factor of each is constant, then the delay will be proportional to: Taking the derivative of this quantity with respect to N and setting it to zero to minimize the delay, the number of stages is: This implies that each stage should be a factor of e (2.718) larger than the previous stage and the delay associated with driving a large current is 2.718*N times larger than the minimum delay of the MOS gate. These stages can add up to an unacceptable delay in providing large amplitude current signals.

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Using this device in conjunction with normal CMOS Area= 8 transistors Delay=1-2 gates Current > 10mA 1/3 area , 1/5 delay, 10 X current

Timing Signals for OTS Driver Circuit time time time