Lecture 33 Syed Mansoor Sarwar

Slides:



Advertisements
Similar presentations
Memory.
Advertisements

Page Table Implementation
EECS 470 Virtual Memory Lecture 15. Why Use Virtual Memory? Decouples size of physical memory from programmer visible virtual memory Provides a convenient.
4/14/2017 Discussed Earlier segmentation - the process address space is divided into logical pieces called segments. The following are the example of types.
CS 153 Design of Operating Systems Spring 2015
CS 333 Introduction to Operating Systems Class 12 - Virtual Memory (2) Jonathan Walpole Computer Science Portland State University.
Memory Management (II)
Memory Management and Paging CSCI 3753 Operating Systems Spring 2005 Prof. Rick Han.
Chapter 3.2 : Virtual Memory
A. Frank - P. Weisberg Operating Systems Simple/Basic Paging.
Memory Management 2 Tanenbaum Ch. 3 Silberschatz Ch. 8,9.
CS 333 Introduction to Operating Systems Class 12 - Virtual Memory (2) Jonathan Walpole Computer Science Portland State University.
1 Tuesday, July 04, 2006 "Programs expand to fill the memory available to hold them." - Modified Parkinson’s Law.
Virtual Memory By: Dinouje Fahih. Definition of Virtual Memory Virtual memory is a concept that, allows a computer and its operating system, to use a.
Operating Systems Memory Management.
8.4 paging Paging is a memory-management scheme that permits the physical address space of a process to be non-contiguous. The basic method for implementation.
1 Chapter 3.2 : Virtual Memory What is virtual memory? What is virtual memory? Virtual memory management schemes Virtual memory management schemes Paging.
Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Operating Systems Lecture 34 Paging Implementation.
IT253: Computer Organization
Operating Systems COMP 4850/CISG 5550 Page Tables TLBs Inverted Page Tables Dr. James Money.
Computer Architecture and Operating Systems CS 3230: Operating System Section Lecture OS-8 Memory Management (2) Department of Computer Science and Software.
8.1 Silberschatz, Galvin and Gagne ©2013 Operating System Concepts – 9 th Edition Paging Physical address space of a process can be noncontiguous Avoids.
8.1 Silberschatz, Galvin and Gagne ©2005 Operating System Principles Implementation of Page Table Page table is kept in main memory Page-table base.
Virtual Memory 1 1.
1 Memory Management. 2 Fixed Partitions Legend Free Space 0k 4k 16k 64k 128k Internal fragmentation (cannot be reallocated) Divide memory into n (possible.
Chapter 91 Logical Address in Paging  Page size always chosen as a power of 2.  Example: if 16 bit addresses are used and page size = 1K, we need 10.
4.3 Virtual Memory. Virtual memory  Want to run programs (code+stack+data) larger than available memory.  Overlays programmer divides program into pieces.
Lecture 7 TLB. Virtual Memory Approaches Time Sharing Static Relocation Base Base+Bounds Segmentation Paging.
Paging Paging is a memory-management scheme that permits the physical-address space of a process to be noncontiguous. Paging avoids the considerable problem.
Page Table Implementation. Readings r Silbershatz et al:
CHAPTER 3-3: PAGE MAPPING MEMORY MANAGEMENT. VIRTUAL MEMORY Key Idea Disassociate addresses referenced in a running process from addresses available in.
COMP 3500 Introduction to Operating Systems Paging: Translation Look-aside Buffers (TLB) Dr. Xiao Qin Auburn University
W4118 Operating Systems Instructor: Junfeng Yang.
Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Operating Systems Lecture 33 Paging Read Ch. 9.4.
Memory Management & Virtual Memory. Hierarchy Cache Memory : Provide invisible speedup to main memory.
COMP 3500 Introduction to Operating Systems Paging: Basic Method Dr. Xiao Qin Auburn University Slides.
COMP 3500 Introduction to Operating Systems TLB and Memory Accesses Dr. Xiao Qin Auburn University Slides.
Basic Paging (1) logical address space of a process can be made noncontiguous; process is allocated physical memory whenever the latter is available. Divide.
Memory Management Virtual Memory.
Non Contiguous Memory Allocation
ECE232: Hardware Organization and Design
CS161 – Design and Architecture of Computer
Lecture Topics: 11/19 Paging Page tables Memory protection, validation
Page Table Implementation
Chapter 8: Main Memory Source & Copyright: Operating System Concepts, Silberschatz, Galvin and Gagne.
Paging and Segmentation
CSCI206 - Computer Organization & Programming
Memory Management 11/17/2018 A. Berrached:CS4315:UHD.
Lecture 6 Memory Management
Paging Lecture November 2018.
CGS 3763 Operating Systems Concepts Spring 2013
Lecture 39 Syed Mansoor Sarwar
Lecture 32 Syed Mansoor Sarwar
Lecture 29: Virtual Memory-Address Translation
CPSC 457 Operating Systems
Lecture 36 Syed Mansoor Sarwar
So far in memory management…
Practical Session 9, Memory
CSE 451: Operating Systems Autumn 2003 Lecture 10 Paging & TLBs
Lecture 37 Syed Mansoor Sarwar
© 2004 Ed Lazowska & Hank Levy
CSE451 Virtual Memory Paging Autumn 2002
CSE 451: Operating Systems Autumn 2003 Lecture 10 Paging & TLBs
Recursive Page Table Lookup in the x86
Lecture 35 Syed Mansoor Sarwar
Lecture 34 Syed Mansoor Sarwar
Translation Lookaside Buffers
CS703 - Advanced Operating Systems
4.3 Virtual Memory.
Virtual Memory 1 1.
Presentation transcript:

Lecture 33 Syed Mansoor Sarwar Operating Systems Lecture 33 Syed Mansoor Sarwar

© Copyright Virtual University of Pakistan Agenda for Today Review of previous lecture Addressing and logical to physical address translation Examples: Intel P4 and PDP-11 Page table implementation Performance of paging Protection in paging 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Review of Lecture 32 MVT Paging Addressing and address translation in paging 1 January 2019 © Copyright Virtual University of Pakistan

Paging Process Address Space Physical Address Space 1 2 1 2 … 3 4 5 6 1 2 … 9 10 15 1 2 3 4 5 6 7 Process Address Space Physical Address Space 1 January 2019 © Copyright Virtual University of Pakistan

Paging Process Address Space Physical Address Space Page Page Table 1 1 2 … 9 10 15 1 2 3 4 5 6 7 Page 3 9 11 … 1 1 2 3 … 7 Page Table Process Address Space Physical Address Space 1 January 2019 © Copyright Virtual University of Pakistan

Paging Process Address Space Physical Address Space Page Table 1 2 3 … 1 2 … 9 10 15 1 2 3 4 5 6 7 9 … 1 2 3 … 7 Page Table Process Address Space Physical Address Space 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Address Translation f 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Paging Example Page size = 4 bytes Process address space = 4 pages Physical address space = 8 frames Logical address: (1,3) = 0111 Physical address: (6,3) = 11011 Page Frame 1 0111 2 3 11011 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Addressing in Paging Logical address space of 16 pages of 1024 words each, mapped into a physical memory of 32 frames. Logical address size? Physical address size? Number of bits for p, f, and d? 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Addressing in Paging No. of bits for p = ceiling [log2 16] bits = 4 bits No. of bits for f = ceiling [log2 32] bits = 5 bits No. of bits for d = ceiling [log2 2048] bits = 11 bits 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Addressing in Paging Logical address size = |p| + |d| = 4+11 = 15 bits Physical address size = |f| + |d| = 5+11 = 16 bits 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Page Table Size Page table size = NP * PTES where NP is the number of pages in the process address space and PTES is the page table entry size (equal to |f| based on our discussion so far). Page table size = 16 * 5 bits = 16 bytes 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Paging in Intel P4 32-bit linear address 4K page size Maximum pages in a process address space = 232 / 4K Number of bits for d = log2 4K = 12 Number of bits for p = 32 - 12 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Paging in PDP-11 16-bit logical address 8K page size Maximum pages in a process address space = 216 / 8K = 8 |d| = log2 8K = 13 bits |p| = 16 – 13 = 3 bits |f| = ? bits 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Another Example Logical address = 32-bit Process address space = 232 B = 4 GB Main memory = RAM = 512 MB Page size = 4K Maximum pages in a process address space = 232 / 4K = 1M 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Another Example |d| = log2 4K = 12 bits |p| = 32 – 12 = 20 bits No. of frames = 512 M / 4 K = 128 K |f| = ceiling [log2 128 K] bits = 17 bits ≈ 4 bytes Physical address = 17+12 bits 1 January 2019 © Copyright Virtual University of Pakistan

Implementation of Page Table In CPU registers OK for small process address spaces and large page sizes Effective memory access time (Teffective) is about the same as memory access time (Tmem) PDP-11 1 January 2019 © Copyright Virtual University of Pakistan

Implementation of Page Table Keep page table in the main memory Page table base register (PTBR) Teffective = 2Tmem Teffective is not acceptable 1 January 2019 © Copyright Virtual University of Pakistan

Implementation of Page Table Use a special, small, fast lookup hardware, called translation look-aside buffer (TLB) Typically 64–1024 entries An entry is (key, value) Parallel search for key; on a hit, value is returned 1 January 2019 © Copyright Virtual University of Pakistan

Implementation of Page Table (key,value) is (p,f) for paging For a logical address, (p,d), TLB is searched for p. If an entry with a key p is found, we have a hit and f is used to form the physical address. Else, page table in the main memory is searched. 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan TLB Logical address: (p, d) f p 1 January 2019 © Copyright Virtual University of Pakistan

Implementation of Page Table The TLB is loaded with the (p,f) pair so that future references to p are found in the TLB, resulting in improved hit ratio. On a context switch, the TLB is flushed and is loaded with values for the scheduled process. 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Paging Hardware 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Performance of Paging Teffective on a hit = Tmem + TTLB Teffective on a miss = 2Tmem + TTLB If HR is hit ratio and MR is miss ratio, then Teffective = HR (TTLB + Tmem) + MR (TTLB + 2Tmem) 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Example Tmem = 100 nsec TTLB = 20 nsec Hit ratio is 80% Teffective = ? Teffective = 0.8 (20 + 100) + 0.2 (20 + 2x100) = 140 nanoseconds 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Example Tmem = 100 nsec TTLB = 20 nsec Hit ratio is 98% Teffective = ? Teffective = 0.98 (20 + 100) + 0.02 (20 + 2x100) = 122 nanoseconds 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Recap of Lecture Logical and physical addresses Address translation Intel P4 example PDP-11 example Implementation of page table Performance of paging 1 January 2019 © Copyright Virtual University of Pakistan

© Copyright Virtual University of Pakistan Operating Systems Lecture 33 Syed Mansoor Sarwar 1 January 2019 © Copyright Virtual University of Pakistan