Sequential Circuits: Latches Adapted by Dr. Adel Ammar

Part 1: Latches

Overview Circuits require memory to store intermediate data Sequential circuits use a periodic signal to determine when to store values. A clock signal can determine storage times Clock signals are periodic Latches are made from logic gates NAND, NOR, AND, OR, Inverter credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

Combinational circuit Sequential Circuits Combinational circuit Flip Flops Outputs Inputs Next state Present state Timing signal (clock) Clock a periodic external event (input) Synchronizes when current state changes happen Keeps system well-behaved Makes it easier to design and build large systems

Simple Latch The problem with the latch formed by NOT gates is that we can't change the stored value. For example, if the output of inverter B has logic 1, then it will be latched forever; and there is no way to change this value.

SR latch The latch is a basic memory element You can see how feedback works by examining the most basic sequential logic components, the SR latch. The “SR” stands for set/reset. The internals of an SR latch are shown below, along with its block diagram. The latch is a basic memory element

3 SR latch The behavior of an SR latch is described by a characteristic table. Q(t) means the value of the output at time t. Q(t+1) is the value of Q after the next clock pulse.

SR latch The SR latch actually has three inputs: S, R, and its current output, Q. Thus, we can construct a truth table for this circuit, as shown at the right. Notice the two undefined values. When both S and R are 1, the SR latch is unstable.

SR latch

S-R Latch with NAND Gates Latch made from cross-coupled NAND gates Sometimes called S’-R’ latch If S = 0 and R = 1: Set state If S = 1 and R = 0: Reset state If S = 1 and R = 1: Hold state If S = 0 and R = 0: Undefined generates unpredictable results S R Q PS Q’ NS 1 U S R Q Q’

S-R Latch R S Q Q’ S R Q(t+1) State Q(t) Hold 1 Reset Set U Undef S R Q(t) Hold 1 Reset Set U Undef S R Q(t+1) State U Undef 1 Set Reset Q(t) Hold S R Q Q’

Clocked SR latch The control input C acts as an enable signal to the latch. When C=0, the S and R inputs have no effect on the latch, so the latch will remain in the same state regardless of the values of S and R. When C=1, the S and R inputs will have the same effect as in the basic SR latch.

Clocked D latch S and R are never equal to 1 at the same time.

Clocked D latch Functional Table Characteristic Table

Clocked JK latch Functional Table JK latch is an improvement over the SR latch in the sense that it does not have any indeterminate states.

Clocked JK latch Characteristic Table Inputs J and K behave like S and R of the SR latch. J and K set and clear the state of the latch, respectively.

Clocked T latch Functional Table a single-input version of the JK latch when T=1, the latch toggles to the complement state when the clock pulse occurs.

Summary: Latches Latches are based on combinational gates (e.g. NAND, NOR) Latches store data even after data input has been removed S-R latches operate like cross-coupled inverters with control inputs (S = set, R = reset) With additional gates, an S-R latch can be converted to a D latch (D stands for data) D latch is simple to understand conceptually When C = 1, data input D stored in latch and output as Q When C = 0, data input D ignored and previous latch value output at Q credential: bring a computer die photo wafer : This can be an hidden slide. I just want to use this to do my own planning. I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20. Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.