Unit 7 Sequential Circuits (Flip Flop)

Slides:



Advertisements
Similar presentations
Introduction to Sequential Logic Design Latches. 2 Terminology A bistable memory device is the generic term for the elements we are studying. Latches.
Advertisements

Give qualifications of instructors: DAP
Latches CS370 –Spring 2003 Section 4-2 Mano & Kime.
Digital Electronics Lecture 7 Sequential Logic Circuit Design.
1 Fundamentals of Computer Science Sequential Circuits.
CHAPTER 3 Sequential Logic/ Circuits.  Concept of Sequential Logic  Latch and Flip-flops (FFs)  Shift Registers and Application  Counters (Types,
CS 151 Digital Systems Design Lecture 19 Sequential Circuits: Latches.
1 Lecture 20 Sequential Circuits: Latches. 2 Overview °Circuits require memory to store intermediate data °Sequential circuits use a periodic signal to.
CPEN Digital System Design Chapter 5 Sequential Circuits Storage Elements and Sequential Circuit Analysis C. Gerousis © Logic and Computer Design.
EET 1131 Unit 10 Flip-Flops and Registers
Digital Logic Design Brief introduction to Sequential Circuits and Latches.
EKT 124 / 3 DIGITAL ELEKTRONIC 1
Sequential Logic Flip-Flops and Related Devices Dr. Rebhi S. Baraka Logic Design (CSCI 2301) Department of Computer Science Faculty.
Latches Section 4-2 Mano & Kime. Sequential Logic Combinational Logic –Output depends only on current input Sequential Logic –Output depends not only.
SEQUENTIAL CIRCUITS USING TTL 74XX ICS
1 Sequential Circuit Latch & Flip-flop. 2 Contents Introduction Memory Element Latch  SR latch  D latch Flip-flop  SR flip-flop  D flip-flop  JK.
FLIP FLOP By : Pn Siti Nor Diana Ismail CHAPTER 1.
ECA1212 Introduction to Electrical & Electronics Engineering Chapter 9: Digital Electronics – Sequential Logic by Muhazam Mustapha, November 2011.
JK Flip-Flop. JK Flip-flop The most versatile of the flip-flops Has two data inputs (J and K) Do not have an undefined state like SR flip-flops – When.
Synchronous Sequential Circuits by Dr. Amin Danial Asham.
Sequential logic circuits
1 Lecture #11 EGR 277 – Digital Logic Ch. 5 - Synchronous Sequential Logic There are two primary classifications of logic circuits: 1.Combinational logic.
Synchronous Sequential Logic A digital system has combinational logic as well as sequential logic. The latter includes storage elements. feedback path.
Sequential Circuit Latch & Flip-flop. Contents Introduction Memory Element Latch  SR latch  D latch Flip-flop  SR flip-flop  D flip-flop  JK flip-flop.
Chapter 6 – Digital Electronics – Part 1 1.D (Data) Flip Flops 2.RS (Set-Reset) Flip Flops 3.T Flip Flops 4.JK Flip Flops 5.JKMS Flip Flops Information.
Chapter5: Synchronous Sequential Logic – Part 1
Synchronous Sequential Circuits by Dr. Amin Danial Asham.
Synchronous Sequential Circuits by Dr. Amin Danial Asham.
Flip-Flop Flip-flops Objectives Upon completion of this chapter, you will be able to :  Construct and analyze the operation of a latch flip-flop made.
Sequential logic circuits First Class 1Dr. AMMAR ABDUL-HAMED KHADER.
Computer Science 210 Computer Organization
Lecture 4. Sequential Logic #1
Dr. Clincy Professor of CS
FLIP FLOPS Binary unit capable of storing one bit – 0 or 1
Flip Flops.
LATCHED, FLIP-FLOPS,AND TIMERS
EI205 Lecture 8 Dianguang Ma Fall 2008.
Computer Organization
Lecture 8 Dr. Nermi Hamza.
FIGURE 5.1 Block diagram of sequential circuit
Digital Design Lecture 9
Synchronous Sequential Circuits
Flip-Flop.
DR S. & S.S. GHANDHY ENGINEENRING COLLEGE
Sequential Logic and Flip Flops
CISE204: Design of Digital Systems Lecture 18 : Sequential Circuits
Latches, Flip-Flops and Registers
Flip Flop.
Computer Science 210 Computer Organization
ECE Digital logic Lecture 16: Synchronous Sequential Logic
Chapter 11 Sequential Circuits.
Sequential logic circuits
Chapter 6 -- Introduction to Sequential Devices
Satish Pradhan Dnyanasadhana college, Thane
Sequential Logic and Flip Flops
Boolean Algebra and Digital Logic
Computer Science 210 Computer Organization
CSC 220: Computer Organization
Synchronous Sequential Circuits
Sequential Circuits: Latches
Reference: Chapter 5 Sequential Circuits Moris Mano 4th Ediditon
Flip-Flops Last time, we saw how latches can be used as memory in a circuit. Latches introduce new problems: We need to know when to enable a latch. We.
CSC 220: Computer Organization COMBINATIONAL CIRCUITS-2
University of Maryland Baltimore County Department of Computer Science and Electrical Engineering   CMPE 212 Laboratory (Discussion 10) Hasib Hasan
Synchronous sequential
Synchronous Sequential
Flip-Flops.
Lecture 14: State Tables, Diagrams, Latches, and Flip Flop
Sequential Digital Circuits
Week 11 Flip flop & Latches.
Presentation transcript:

Unit 7 Sequential Circuits (Flip Flop) College of Computer and Information Sciences Department of Computer Science CSC 220: Computer Organization Unit 7 Sequential Circuits (Flip Flop)

Overview SR Latch SR Latch SR Latch with Control Input D Latch Unit 7: Sequential Circuits Overview SR Latch SR Latch SR Latch with Control Input D Latch Clock and Synchronization Flip-flops Positive edge-triggered D Flip-flop JK &T Flip-flop Direct Inputs Chapter-4 M. Morris Mano, Charles R. Kime and Tom Martin, Logic and Computer Design Fundamentals, Global (5th) Edition, Pearson Education Limited, 2016. ISBN: 9781292096124

SR Latch The SR Latch, can be considered as one of the most basic sequential logic circuit possible. This simple circuit is basically a one-bit memory bistable device. It has two inputs, S: will “SET” the device (meaning the output Q = “1”) R: will “RESET” the device (meaning the output Q = “0”) Output Q is always complement of Q

SR Latch The SR Latch, is build with two cross-coupled NAND gate. Q 1 No Change !

Give Examples

The output of the flip flop would always change on every pulse applied to this data input. To avoid this an additional input called the “CLOCK” or “ENABLE” input is used to isolate the data input from the flip flop’s latching circuitry after the desired data has been stored. The effect is that D input condition is only copied to the output Q when the clock input is active. This then forms the basis of another sequential device called a D Flip Flop.

It can be seen from the frequency waveforms above, that by “feeding back” the output from Q to the input terminal D, the output pulses at Q have a frequency that are exactly one half ( ƒ/2 ) that of the input clock frequency, ( ƒIN ). In other words the circuit produces frequency division as it now divides the input frequency by a factor of two (an octave) as Q = 1 once every two clock cycles.

Direct Inputs Flip-flops often provides special inputs PS, PR for setting and resetting them: Independent of clock input Initializes the flip-flop PS PR CK J K Q(t+1) 1  Q(t) Q(t) X Undefined

D Flip Flops as Data Latches A data latch can be used as a device to hold or remember the data present on its data input, thereby acting a bit like a single bit memory device and IC’s such as the TTL 74LS74 or the CMOS 4042 are available in Quad format exactly for this purpose. By connecting together four, 1-bit data latches so that all their clock inputs are connected together and are “clocked” at the same time, a simple “4-bit” Data latch can be made as shown below.